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zero delay timing after constrained optimization in FPGA?

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jkfoo

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synopsys directive for delay optimization

Hi,

I instantiate a Coregen generated adder in my design, and synthesized using FPGA Express. The timing report shows zero timing delay on this particular adder, which is not correct. The actual delay can only be reported after place and route. Anyone knows why? Thx.
 

skynet

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Hi jkfoo,

Before you start to synthesize a design using FPGA Sythesize tools, you need to configure all the constraint such as design speed, fan-in, fan-out, and etc. other wise the synthesizer will show zero delay path if you did not configure the constraint.

regard,
SkyNet
 

Nobody

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Coregen wrape the xilinx primitive cell inside , fpga-express take it as a black-box and no timing info provide so assuming 0 delta delay.
 

jkfoo

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Thanks for the reply. Do you mean there is no way that the fpga-express can report the timing of the coregen cell. If that is the case, how could the designer knows whether the design has met timing before proceeding to place and route? How about other tools like synplify and leonardo, can they report the correct timing?
 

Nobody

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What those fpga compilers has the vendor timing library to caculate the "primitive cell" delay by the 2 dimention ( driving , load ) . The coregen add some compiler directive like // synthesis black_box , synopsys translate_off to tell compiler to take the macro as black box , This blackbox have no timing library info , compiler ignore it and set it to 0 delay time . Look your compiler install dir/lib/<vendor device>/ to see what primitive cells timing lib provide, If you would like to see the timing report , delete those compiler directive or flatten your macro adder , report timing -from input -to output .
 

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