jkfoo
Member level 1

synopsys directive for delay optimization
Hi,
I instantiate a Coregen generated adder in my design, and synthesized using FPGA Express. The timing report shows zero timing delay on this particular adder, which is not correct. The actual delay can only be reported after place and route. Anyone knows why? Thx.
Hi,
I instantiate a Coregen generated adder in my design, and synthesized using FPGA Express. The timing report shows zero timing delay on this particular adder, which is not correct. The actual delay can only be reported after place and route. Anyone knows why? Thx.