I have synthesized a design which includes the wire-load delay model. After exteracting the SDF file using Synopsys DC, I found zero-delay for all interconnections in sdf file while the gates have delays. My question is why the delay of the interconnection is zero even if I have included the wire-load model and what is wrong in my setup ?
My SDF file is somehting like this for all interconnections:
(INTERCONNECT U953/Y U1344/B0 (0.000:0.000:0.000))
(INTERCONNECT U723/Y U1344/B1 (0.000:0.000:0.000))
(INTERCONNECT U723/Y U1344/A0N (0.000:0.000:0.000))
(INTERCONNECT U1341/Y U1343/A0 (0.000:0.000:0.000))
In fact, I want to see the effect of interconnection delay on the my simulation outputs before P & R. I know these delays are not accurate at all, but it still gives me some hints about the timing of my design. It is very weird to me to see the zero-delay interconnection in SDF file. In such case, the use of Wire-load seems to be pointless.
my first suggestion would be to report timing in DC with and without your wireload model and see if it makes any change. it's possible it doesn't, some flag is off, the tool was expecting something else instead, etc..