Xilinx Packages - need help with the code, error occurs

[GreenP]

Xilinx Packages

Could anyone please help as I am experiencing difficulties being able to use a package that I have created in Xilinx. The package created is a simple not gate as I would like to be able to get my head around the concept of creating packages and then implementing them in the Xilinx development. The code used for the package is shown, this is saved into a file labeled PJK_my_functions, the code implementing the package is also shown
[library IEEE;
use IEEE.STD_LOGIC_1164.all;
------------------------------------------------------------------------------
package not_pkg is

procedure not_gate (a_0: in std_logic; x_0: out std_logic);

end not_pkg;
--------------------------------------------------------------------------------
package body not_pkg is

procedure not_gate (a_0: in std_logic; x_0: out std_logic) is

begin

x_0 := not a_0;

end not_gate;

end not_pkg;]

[ library IEEE;
Library PJK_my_functions;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use PJK_my_functions.not_pkg.ALL;

entity gate_combination is
Port ( a_1 : in STD_LOGIC;
x_1 : out STD_LOGIC);
end gate_combination;

architecture Behavioral of gate_combination is

begin

Z_1 : not_gate (a_0 => a_1, x_0 => x_1);

end Behavioral;]

The error that I am recieving is:

Line 17. Actual, Signal 'x_1', associated with Formal Variable, Variable 'x_0', is not a Variable. (LRM 2.1.1)

I would really like a bit of advice on this
Thanking you in advance[/quote]