Jan 27, 2014 #1 W win2010 Member level 1 Joined Sep 30, 2010 Messages 35 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,605 Hi, I`m working with too many signals and variable(VHDL), while synthesizing it taking long time and also not completing. Ex: signal Buf1(64799 downto 0); signal Buf2(64799 downto 0); What is the alternative to this problem and how to design such complected buffers.. Thank you.. Vinayak
Hi, I`m working with too many signals and variable(VHDL), while synthesizing it taking long time and also not completing. Ex: signal Buf1(64799 downto 0); signal Buf2(64799 downto 0); What is the alternative to this problem and how to design such complected buffers.. Thank you.. Vinayak
Jan 27, 2014 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 Are you deliberatly trying to have so many registers, or did you intend for these signals to infered memories? Massive arrays that create registers will always take a long time to compile. If you did intend to have a massive register array - why?
Are you deliberatly trying to have so many registers, or did you intend for these signals to infered memories? Massive arrays that create registers will always take a long time to compile. If you did intend to have a massive register array - why?
Jan 27, 2014 #3 W win2010 Member level 1 Joined Sep 30, 2010 Messages 35 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,605 I`m designing interleaver so need to store 64800 bits and also do circular shift using formula and output those values bit by bit....
I`m designing interleaver so need to store 64800 bits and also do circular shift using formula and output those values bit by bit....
Jan 27, 2014 #4 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 That still doesnt really explain anything - why cant you use a memory?
Jan 27, 2014 #5 W win2010 Member level 1 Joined Sep 30, 2010 Messages 35 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,605 If i go for memory(RAM) then complexity increases and also delay increases.... Is their any effective solution for this...?
If i go for memory(RAM) then complexity increases and also delay increases.... Is their any effective solution for this...?
Jan 27, 2014 #6 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 Yes - increase complexity and delay. It sound like you dont really understand FPGA architecture. What is wrong with a longer pipeline delay?
Yes - increase complexity and delay. It sound like you dont really understand FPGA architecture. What is wrong with a longer pipeline delay?
Jan 27, 2014 #7 W win2010 Member level 1 Joined Sep 30, 2010 Messages 35 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,605 I`m beginner not so much good at coding.. Now trying to understand things. Really i face difficultly with using RAM so only asked. Thank you for kind reply...
I`m beginner not so much good at coding.. Now trying to understand things. Really i face difficultly with using RAM so only asked. Thank you for kind reply...