Xilinx not synthesizing- taking long time

[win2010]

Hi,
I`m working with too many signals and variable(VHDL), while synthesizing it taking long time and also not completing.

Ex: signal Buf1(64799 downto 0);
signal Buf2(64799 downto 0);

What is the alternative to this problem and how to design such complected buffers..


Thank you..
Vinayak

 

[TrickyDicky]

Are you deliberatly trying to have so many registers, or did you intend for these signals to infered memories?
Massive arrays that create registers will always take a long time to compile.

If you did intend to have a massive register array - why?

 

[win2010]

I`m designing interleaver so need to store 64800 bits and also do circular shift using formula and output those values bit by bit....

 

[TrickyDicky]

That still doesnt really explain anything - why cant you use a memory?

 

[win2010]

If i go for memory(RAM) then complexity increases and also delay increases....

Is their any effective solution for this...?

 

[TrickyDicky]

Yes - increase complexity and delay.
It sound like you dont really understand FPGA architecture. What is wrong with a longer pipeline delay?

 

[win2010]

I`m beginner not so much good at coding.. Now trying to understand things. Really i face difficultly with using RAM so only asked.

Thank you for kind reply...