neanton28
Newbie level 5
Greetings! Looking for best practices in fpga design. I have FPGA that gets data BT.656 from ADV7180 decoder - 8 bit parallel interface for data and LLC (clock for synchronization 27 MHz). Data it valid on rising edge. My FPGA stores this data to internal BSRAM, makes some modification to image and outputs it from BSRAM to BT.656 encoder ADV7391. Processing logic is sourced by separate clk multiplied by PLL.
Right now, incoming LLC from ADV7180 is used to trigger saving into BSRAM, and same time is output to ADV7391. My internal logic checks all the time what value LLC has now (low or high).
I am interested which of designs is better to use? Now LLC is connected to output in FPGA with branch to processing logic
Or LLC should be separate wire on board and connect directly ADV7180 with ADV7391 with branch to FPGA:
Right now, incoming LLC from ADV7180 is used to trigger saving into BSRAM, and same time is output to ADV7391. My internal logic checks all the time what value LLC has now (low or high).
I am interested which of designs is better to use? Now LLC is connected to output in FPGA with branch to processing logic
Or LLC should be separate wire on board and connect directly ADV7180 with ADV7391 with branch to FPGA: