layaghi
Member level 3
I'm using xilinx dds core in a spartan3 fpga.
I have already make a signal with a desired frequency.
since I change the valuse of "A", "DATA" and "WE" inputs in my VHDL code the output frequency does not changes.
how could I make the output frequency to sweep?
I have already make a signal with a desired frequency.
since I change the valuse of "A", "DATA" and "WE" inputs in my VHDL code the output frequency does not changes.
how could I make the output frequency to sweep?