xilinx constraint declaration need help !

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Matrix_YL

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xilinx multiplier synthesis block vs lut

Hi all


I spend too much block multiplier on my design ,so I want to use some of them by lut .

I do my constraint according to xilinx cdg.pdf .
Specify as follows:
// synthesis attribute mult_style [of] {module_name|signal_name} [is]
{auto|block|lut|pipe_lut|pipe_block|CSD|KCM};

but the synthesized report generated by two block multiplier

what's wrong with my HDL ? or Mybe I misunderstand the usage of xilinx constraint declaration .can you help me solve this problem ?
thank you very much !
 

set as top module xilinx

Remove the {} ?
So it looks like

Code:
// synthesis attribute mult_style of result_1 is lut;
{} is typically used to group choices together in a syntax description.
 

    Matrix_YL

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google groups mult_style

Hi tkbits
I do it according to what you indicated,but fail to implement!
 

cdg.pdf xilinx

tkbits instructions are correct. You didn't remove all the {}.
Here is a working module:

Code:
module multiplier (result_1, result_2, a, b, c, d);
  input  [3:0] a, b, c, d;
  output [7:0] result_1, result_2;

  assign result_1 = a * b; // synthesis attribute mult_style of result_1 is lut;
  assign result_2 = c * d; // synthesis attribute mult_style of result_2 is block;
endmodule
 

    Matrix_YL

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assign synthesis to lut

Hi tkbits
I do it according to what you indicated,but fail to implement!
It's my mistake.


thanks for your help
 

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