but the synthesized report generated by two block multiplier
=============================================================
* HDL Analysis *
=========================================================================
Analyzing top module <multiplier>.
Module <multiplier> is correct for synthesis.
"multiplier.v" line 36: Cannot find <{result_1}> in module <multiplier>, property <mult_style> with Value <{lut}> is ignored.
"multiplier.v" line 38: Cannot find <{result_2}> in module <multiplier>, property <mult_style> with Value <{block}> is ignored.
Set property "resynthesize = true" for unit <multiplier>.
what's wrong with my HDL ? or Mybe I misunderstand the usage of xilinx constraint declaration .can you help me solve this problem ?
thank you very much !
Hi tkbits
I do it according to what you indicated,but fail to implement!
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HDL Analysis *
=========================================================================
Analyzing top module <multiplier>.
Module <multiplier> is correct for synthesis.
"multiplier.v" line 36: Cannot find <{result_1}> in module <multiplier>, property <mult_style> with Value <lut> is ignored.
"multiplier.v" line 38: Cannot find <{result_2}> in module <multiplier>, property <mult_style> with Value <block> is ignored.
Set property "resynthesize = true" for unit <multiplier>.