Matrix_YL
Advanced Member level 4

xilinx multiplier synthesis block vs lut
Hi all
I spend too much block multiplier on my design ,so I want to use some of them by lut .
I do my constraint according to xilinx cdg.pdf .
thank you very much !
Hi all
I spend too much block multiplier on my design ,so I want to use some of them by lut .
I do my constraint according to xilinx cdg.pdf .
Specify as follows:
// synthesis attribute mult_style [of] {module_name|signal_name} [is]
{auto|block|lut|pipe_lut|pipe_block|CSD|KCM};
but the synthesized report generated by two block multipliermodule multiplier(
//Output
result_1,result_2,
//Input
a,b,c,d
);
input[3:0] a;
input[3:0] b;
input[3:0] c;
input[3:0] d;
output[7:0] result_1;
output[7:0] result_2;
assign result_1= a*b; // synthesis attribute mult_style of {result_1} is {lut};
assign result_2= c*d; // synthesis attribute mult_style of {result_2} is {block};
endmodule
what's wrong with my HDL ? or Mybe I misunderstand the usage of xilinx constraint declaration .can you help me solve this problem ?=============================================================
* HDL Analysis *
=========================================================================
Analyzing top module <multiplier>.
Module <multiplier> is correct for synthesis.
"multiplier.v" line 36: Cannot find <{result_1}> in module <multiplier>, property <mult_style> with Value <{lut}> is ignored.
"multiplier.v" line 38: Cannot find <{result_2}> in module <multiplier>, property <mult_style> with Value <{block}> is ignored.
Set property "resynthesize = true" for unit <multiplier>.
thank you very much !