Xilinx 7.1i version "Cannot synthesis operator DIV&quot

[sunky]

need help, please

hello friends, i am a beginner in VERILOG, my project is based on calculating modular multiplication value (Z=X*Y mod M).
It needs the div operator / to calculate the quotient value.
I am working in Xilinx 7.1i version.
While synthesis it gives the following error "Cannot synthesis operator DIV"
Anyone, please help me in fixing this error.

 

[muni123]

Re: need help, please

Hi Sunky,

The best way we can make this work is to move on to the latest version of Xilinx ISE.
Xilinx ISE 9.1i supports DIV operator to my knowledge. Please check.

Thanks!!