hello
i have 20 mhz input and i want to multiply this frequence to 50 Mhz to provide in output.
i'm a begineer and i need to know how i can do this in vhdl or verilog.
Regards
You'll need a PLL to create a 50MHz clock from a 20 MHz clock. If this code is aimed towards a FPGA you can use one of the PLL ips available with your vendor. If not you could search this forum and you'll see lots of posts talking about implementing a PLL in verilog.
If you have a 7ns version or faster type of this CPLD, you maybe able to create 40 and 80MHz clocks from your 20MHz, but it will not be a stable creation and it will be highly unreliable.