Wrong BW simulation reports of analog switch

[billchen]

I designed an analog switch. The switch is T type, which is composed by 2 T-gate and a NMOS.
The PMOS W/L is about 35000um/0.5um and the NMOS is 7000um/0.5um. That means the on resistor is very low, the test results is about 2.5ohm; but the paracitic capacitor is very large.
The BW simulaiton results of this analog switch is about 2G, but the test results is only 30MHz. It is a very big difference.
I thinks maybe 3 reasons reasons results in this differenc.
1, Model is not accurate.
2, layout parasitic devices.
3,Test equipment. (Other products can get 300M BW test results, so i think this is not main reason.)

I think ,the layout parasitic devices should decrease the BW , but should not effects so obviously. It differenc is about 70 times.

So, who can give me some suggestions about this issue. Thanks.

 

[FvM]

Re: BW of analog switch

Don't you think it would be meaningful to verify the bandwidth determining parameters individually? From the information you provided up to now, we just could think: The guys apparently don't know what they are doing in IC design.

Circuit inductances (e.g. from bond wires) may a sufficient explanation for the results. They should be 1. simulated from the start and 2. identified in the test device by an impedance measurement

 

[Colbhaidh]

Re: BW of analog switch

Models should be fairly accurate (given it's inputs),
Did you model the circuit accurately,
i.e. :
Capacitance from multi fingered transistor that made up the T switch?
Did you include parasitic capacitance from layout?
Are your interconnect capacitances being modelled?
Is the dielectric cconstant for the process correct ?
Could the T switch matching cause a problem (more likely) ?

 

[billchen]

Re: BW of analog switch

To FvM
Thanks for your reply.
Actually,i think we can simplify the model of T-type analog switch to only a low pass filter, which only includes a resistor and a cap.The resistor is the on resistance of the switch.And the cap is the equivalent cap of the output node.

We can get the test results of the cap between output node and Ground.It is about 230pF. The test results of on-resistance is 2.5ohm. From this point, the BW should be about 280MHz. But the test results is only about 28MHz.

Thanks

I will post more test results later.

Added after 7 minutes:

To Colbhaidh,
Thanks for your reply.

Capacitance from multi fingered transistor that made up the T switch?
Did you include parasitic capacitance from layout?
Are your interconnect capacitances being modelled?
-------I have run the simulation with extracted cap,include the interconnect cap. The simulation results in worst case is about 200M.

Is the dielectric cconstant for the process correct ?
------Is this will effect the value of cap?

Could the T switch matching cause a problem (more likely) ?
-----I do not understand this question.Could you explain more clearly.
Thanks

Added after 22 minutes:

To Colbhaidh,
Thanks for your reply.

Capacitance from multi fingered transistor that made up the T switch?
Did you include parasitic capacitance from layout?
Are your interconnect capacitances being modelled?
-------I have run the simulation with extracted cap,include the interconnect cap. The simulation results in worst case is about 200M.

Is the dielectric cconstant for the process correct ?
------Is this will effect the value of cap?

Could the T switch matching cause a problem (more likely) ?
-----I do not understand this question.Could you explain more clearly.
Thanks

 

[billchen]

Re: BW of analog switch

For a simplest T-gate, it can be equvalent to Fig1.
R1 is the paracitic resistance of the metal. The R2 is the on resistance of the T-gate. R2 is several times than R1.
C1 equals to C2, they are the paracitic cap of the cgs and cgd.
C3 is the paracitic cap between Drain and Source.
In the low frequency, the 1/sc3 is << R2. In the test conditions, the load resistance is 50ohm, and R2<< 50ohm, so we can cancel 50ohm load resistance.
The equvalent circuit is Fig2. Actually, the liberal equvalent circuit can be fig3.

So i think , we can test the on resistance R2 of the T-gate ,and the output capcitor C2||C1. Then we can get the main pole.
But ancturally, the test results of BW and the caculation results is more different. I do not know why?

Who can provide any hints about this analysis?
Thanks

 

[rf_ray]

Re: BW of analog switch

Did you use package or on wafer measurement? Make proper calibration if needed.

 

[billchen]

Re: BW of analog switch

rf_ray
Not wafer test, it package test. Made calibration before every test.

 

[gksivas]

Re: BW of analog switch

i am wonder about W/L ratios. actually i don't no about analog switch. but width for PMOS IS 35000um and for NMOS is 7000um. ithis much of width switch requires. please clarify, is that values are correct.