Writing values into memory and reading those values. Timing Issue!!!

module mem_test(input logic clk, output logic read, write, output logic [4:0] addr, output logic [7:0] data_in, input logic [7:0] data_out);
timeunit 1ns;
timeprecision 1ps;
bit debug=1'b0;
//logic [7:0] rdata_out;

task write_mem(input logic [4:0] waddr, input logic [7:0] wdata_in, input logic debug);
	@(negedge clk) begin
		addr <= waddr;
		data_in <= wdata_in;
		write <= 1'b1;
		read <= 1'b0;
	end

	unique if(debug) begin
		$display("addr=%b, data_in=%b", waddr, wdata_in);
	end
endtask

task read_mem(input logic [4:0] raddr, input logic debug);
	@(negedge clk) begin
		#10 addr <= raddr;
		read <= 1'b1;
		write <= 1'b0;
		//#2 rdata_out <= data_out;
	end
	//rdata_out <= data_out;
	
	unique if(debug) begin
		$display("addr=%b, data_out=%b", raddr, data_out);
	end

endtask 

initial begin
//genvar i, j, k, l;
for(int i=0;i<=31;i++) begin
	write_mem(i,8'd0,1'd1);
end

begin
	 for(int j=0;j<=31;j++) begin
		read_mem(j,1'd1);
	 end
end


for(int k=0;k<=31;k++) begin
	write_mem(k,k,1'd1);
end

begin
	for(int l=0;l<=31;l++) begin
	read_mem(l,1'd1);
	end
end

#500 $finish;
end

endmodule