Writing Test Bench in System Verilog

[kunal1514]

Hi All,

I am going to make a test enviornment in System Verilog.

for this i need this book please make it as soon as possible.

 

[aji_vlsi]

Hi All,

I am going to make a test enviornment in System Verilog.

for this i need this book please make it as soon as possible.

I would rather simply use the technical documentation that ships along with the tool that supports SystemVerilog to get quickly started. I've seen the one from SNPS, quite nice and also saw some in www.cdnusers.org. You can also download AVM cookbook from mentor.com that has full examples.

Now for a real quick start, my company offers quick start trainings in this area - Functional Verification, SystemVerilog for Designers (Design + Assertions) and SystemVerilog for Verification engineers. Send email to cvc.training if you need more info on that. Check out our website for more details: www.noveldv.com

HTH
Ajeetha, CVC
www.noveldv.com

 

[sanjay11]

https://www.mentor.com/products/fv/_3b715c/

 

[mssajwan]

Hi,

Its better to use the technical documentation provided along with the tool.as thats the best method to learn it fast & even u can be able to use the most supported constructs by the tool.