writing synthesizable RTL for async set,async clear flipflop

[sivasankar]

Hi,
I am designing ripple counter to generate a slow clock for low power design, I would like to know how do I design verilog RTL for loading pre determined value to all FF's, so that MSB bit go as a clock.

right now I am writing RTL something like this

always @(posedge clk or negedge reset_n or negedge load)
if(reset_n == 1'b0)
ff0 <= 1'b0;
else if (load == 1'b0)
ff0 <= clk_div[0];
else
ff0 <= ~ ff0;

always @(posedge ff0 or negedge reset_n or negedge load)
if(reset_n == 1'b0)
ff1 <= 1'b0;
else if (load == 1'b0)
ff1 <= clk_div[1];
else
ff1 <= ~ff1;

:
:

I am wondering, having multiple "OR" in sensitivity list in clock process is synthesizable?.
Does any body come across any problem, by having such a coding style?.

How will I avoid glitches in async ckt?. while loading some glitches are occuring in ff0..


Please give me solution?

Thanks
Siva

 

[vinod_g]

Re: writing synthesizable RTL for async set,async clear flip

Some tools may not take more than 2 events in the sensitivity list.so i think its the problem for u

 

[sivasankar]

Re: writing synthesizable RTL for async set,async clear flip

How do we deal with such a design requirement?
Siva