Hi,
On studying Xilinx ref manuals,this is what i understood:
There are three different interfaces that are supported by the generated memory controller.These are the Advanced eXtensible Interface 4 (AXI4) Slave Interface, the User Interface(UI) and the native interface.
As of now the AXI4 slave interface for the MIG is available only in Verilog,and not VHSIC HDL (VHDL) and i'm designing in vhdl.So,i'm going with UI.
In UI,how can we change ui signals like app_addr,app_wdf_data.By default app_wdf_data gets address as its data.How to change these ?
I tried changing DATA_PATTERN & CMD_PATTERN but this has no effect on app_* signals.