er.akhilkumar
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Hello all,
If anyone knows how can we design WRITE ONCE type memory elements using VHDL or Verilog which means, "The register can be written only one time during the device lifetime, the value is kept after power cycle or any type of reset", please help.
Thanks and Regards,
Akhil Kumar
If anyone knows how can we design WRITE ONCE type memory elements using VHDL or Verilog which means, "The register can be written only one time during the device lifetime, the value is kept after power cycle or any type of reset", please help.
Thanks and Regards,
Akhil Kumar