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Word Line Modeling in SRAM

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020170

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Word line is made of Salicide polysilicon in SRAM.

Salicide process makes polysilicon reduce its resistance.

Even though, Salicide Polysilicon have larger sheet resistance than Metal Line.

To make SRAM control command, I realized I have to consider delay in word line.

Of course, the delay is due to polysilicon sheet resistance, about 10 ohm/square.

And I consider capacitance between metal line & word line, too.

As a result, I modeling SRAM cell like this.

Is there any problem in my cell modeling?

If there is some my mistake, Don't hesitate to catch up my mistake.

Thanks!
 

You have to consider the load of all not-selected cell on the WL. Second the distributed load effect could be worse for the last cell. So with a 4 or 8 tap model you will be close to reality.

In cadence spectre you can use a e.g. M=64 for subcircuits to simplify the load modelling of many parallel connected cells.
 

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