WLM & STD libs - how many required?

[ivlsi]

Hi All,

As for WLM, for how many PVT corners are they usually created?

As for STD libs, there is usually a set of three - for min, max and typ delays. Is the same for WLMs? Does each STD lib include WLM for the given corner (min/max/typ)?

Thank you!

 

[oratie]

The one STD lib may include many WLMs. They have nothing with PVT corners. One WLM may be more pessimistic in RC estimation, another one is more optimistic. It depends on library vendor. Even more, you may create your own WLM, which may be more accurate for your design.

 

[ivlsi]

you may create your own WLM

What's the flow? How should the first-run synthesis (without WLM or with Zero-WLM) be done? Should the clock be over-constrained with a margin of 20% for the first run? What about clock uncertainly? What about other constraints?

Thank you!