when I use DC and RC(RTL compiler) for a same design, the gate count result is no much different, but wire area differ too much.
Now I'm evaulate these two tools, and wire area is the one that I need to concern?
Less wire area, more routable in layout period?
Deppending on your .lib file, you have there a wire load model(s). Wire area is an estimated value during synthesis.
IF you want to be more accurate in your evaluation, you need a wire load model, for the design you are using, coming from the P&R tool.
Hope this helps!
tavidu said:
when I use DC and RC(RTL compiler) for a same design, the gate count result is no much different, but wire area differ too much.
Now I'm evaulate these two tools, and wire area is the one that I need to concern?
Less wire area, more routable in layout period?