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Wire area difference when using DC and RC for the same design

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tavidu

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when I use DC and RC(RTL compiler) for a same design, the gate count result is no much different, but wire area differ too much.
Now I'm evaulate these two tools, and wire area is the one that I need to concern?
Less wire area, more routable in layout period?
 

Atre

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Re: wire area

Hello,

Deppending on your .lib file, you have there a wire load model(s). Wire area is an estimated value during synthesis.
IF you want to be more accurate in your evaluation, you need a wire load model, for the design you are using, coming from the P&R tool.

Hope this helps!

tavidu said:
when I use DC and RC(RTL compiler) for a same design, the gate count result is no much different, but wire area differ too much.
Now I'm evaulate these two tools, and wire area is the one that I need to concern?
Less wire area, more routable in layout period?
 

jingli888ca

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wire area

A wire load model helps, but eventually it is decided by the P&R tool and your floorplan.

Also, you should worry about the certain instantiated modules, if there are a lot of congestion then it is better to resolve it from RTL phase.
 

Hards

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Re: wire area

read this u will clear
 

newcpu

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wire area

It is a paper from SNUG.
 

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