will a case statement work inside a for loop ( vhdl)

[ramz]

case statements in vhdl

for i in 0 to 3 loop

case(i)
when 1 => some statement executed
when 2 =>
when 3 =>
when others =>
end case
end loop

i tried to use like this, but does not work.. any suggestions appreciatedd

 

[sval]

for loop within case statement in vhdl

try this

process(clk,rst,ena)
	begin 
		if (rst = '1') then
			for i in 0 to 2 loop
				case (i) is
					when 0 =>  
						
					when 1 =>  
						
					when 2 =>
						
				end case;	
			end loop; 
		elsif (rising_edge(clk) and ena = '1') then
			for i in 0 to 2 loop
				case (i) is
					when 0 =>  
						
					when 1 =>  
						
					when 2 =>
						
				end case;	
			end loop; 
		end if;
	end process;

 

[FvM]

loop case statement vhdl

What do you mean with "but does not work". It's legal VHDL syntax and thus basically works (if you supplement the missing ";" delimiters).

On the other hand, as written above , the code is completely meaningless (also the expanded code suggested by sval).

You can simply write a sequence of statements without the for loop iteration scheme and the case construct, it has the same effect.
But it may have a purpose in a more complex iteration scheme.