Is it possible that as you increase the current your MN4,5 transistors go into triode and become just like resistors? Than your output current mirror changes to the mirror MN3-MN0 with MN0 being degenerated by MN5. The ration of MN3 to MN0 is 1:8 and your output current saturates at about 60uA, maybe accounting for the degeneration.
Dear Suta,
Recently I read many papers about this issue,
I found the solution for this, that is the only way is to bias the diode transistor with a current that track the input change, one other simple solution is given in the paper below, I have tried the latter one and it prooved itself as a good solution,
**broken link removed**
please let me know if you can not access the paper but basically here is the circuit
In the steady state DC operation the capacitor CBat is open and the biasing voltage VCN appears on the gate terminal of M3c M4c because the no current will pass through the huge pseudo resistor MR2. in the transient, this capacitor will hold the voltage and will not discharge quickly so it can keep M3C and M4C in the saturation region of any amount of input current
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Dear Suta,
Ipresent below the mirror circuit with the above mentioned solution, for the purpose of comparesion I have also shown the classical one, you can see clearly how the mirror with the Cbat can mirror higher value of input current while the diode biase transistor is fixed by the current in either cases
I would noted here, for normal Opamp or OTA even the calssical one can work fine at the output stage since the current is not gonna to change in more than two orders, howver, for a circuit with adaptive biasing tail current the classical one will fail to mirror the current for a certain level then limits the slew rate below what is expected to be, hence the second circuit will be necessary to sove this problem