actually ..i m working on ASIC design flow during my internship ...i designed RTL of time to digital converter in VHDL in ise(xilinx software) without using IO pads , then after simulation synthesis of rtl is done on DESIGN COMPiLER (synopsys) , where i get : slack (met) : 39998.21ns , total cell area : 10171.224023 , total dynamic power : 34.9620nw , cell leakage power : 20.3732 nw
RESULTS of RTL design with IO pADS : slack (met) : 39998.60ns , total cell area : 185904.372275 , total dynamic power : 97.7921nw , cell leakage power : 227.5925 nw
actually my mentor told me that ..for designing purpose.... RTL with IO pads is good ..