why we use IO pad for chip designing

[alokkmr18]

hello every one...
thanks in advance

my ques :
1) why we use IO pads when we go for chip designing from RTL to LAyOUT level ...

2) why we use give single inputs to io pads & taking single output from IO pads.

 

[rca]

IO pads could drive more capacitance.
1) I don't understand, you should simulated the RTL with IO pads.
2) ? dont understand your txt

 

[alokkmr18]

actually ..i m working on ASIC design flow during my internship ...i designed RTL of time to digital converter in VHDL in ise(xilinx software) without using IO pads , then after simulation synthesis of rtl is done on DESIGN COMPiLER (synopsys) , where i get : slack (met) : 39998.21ns , total cell area : 10171.224023 , total dynamic power : 34.9620nw , cell leakage power : 20.3732 nw

RESULTS of RTL design with IO pADS : slack (met) : 39998.60ns , total cell area : 185904.372275 , total dynamic power : 97.7921nw , cell leakage power : 227.5925 nw

actually my mentor told me that ..for designing purpose.... RTL with IO pads is good ..

 

[rca]

And what is your question?

 

[alokkmr18]

my ques : why we use io pad for designing ,
For chip designing , is it necessary to use IO pads , can't we go with our RTL design up to layout becoz i above mention in my previous post timing, Area & power with or without IO
IO pad will increase these timing,Area & power factor . for chip we are design , that should be less timing ,less area consumes & less power dissipation .

and what are advantage of io pad for chip designing ..

 

[rca]

std cell coul not drive a PCB wire, or connection between two chips on a PCB.
The IO are stronger buffers, and also special ESD structure.
The bound pad are not mandatory, only the active pads.