Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Tri state devices have enable signals which can cause either a bus contention or a bus float fault. As a result when ATPG analysis is done on them, the logical values on these can result in the enable line faults being undetected.