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why Verdi/0-In Check/specman not NT-platform ?

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Full Member level 5
Full Member level 5
Apr 19, 2002
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passing time scale from specman

I am wondering why Nov@s' Verd!, 0-In Check, Verisity's $pecman Elite
and so on, do not support the NT platform ?
(Also, m0delsim's c-debug...)

When c-debug first appeared at m0delsim 5.6 release,
I thought the reason is because it just a beta version.

But till now, the 5.7 release, the c-debug feature is still only
available on UNIX and Linux environment.
So I guess if it use the C-compiler,such gcc or cc on the UNIX,
and for NT, it may be much complex to do :?:

I hope in the later release, c-debug & Verd! may work on NT :eek:
(Is it possible ?)

By the way, does $ynopsys' VC$' direct-C works on NT ?

M0del-tech has announced it will support SystemVerilog.
And SystemVerilog has the ability to run Verilog/VHDL/C
mixed-language simulation.
In this prorgress, maybe SystemVerilog simulator will only be
available on UNIX and Linux operating system ?


Member level 2
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Jul 17, 2001
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binding vhdl two-d arrays in systemverilog

Verisity's $pecman Elite have linux version, the same with novas.


Member level 3
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Apr 4, 2003
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vsim foreign attribut

-----------snippet for SYSTEM-C

ModelSim 6.0 supports SystemC on Windows. sccom uses MinGW gcc 3.2.3 for compiling the SystemC source code. C-Debug is supported on Windows with MinGW gdb 6.0.

--------- full snippet

Release Notes For ModelSim SE/PE/LE 6.0 Beta

Copyright Model Technology, a Mentor Graphics
Corporation company, 2004 - All rights reserved.

Jun 04 2004


Product Installation and Licensing Information
For brief instructions about product installation please visit the "install_notes" file on the Model Technology web site. The install_notes file can be viewed at:
For detailed information about product installation, supported platforms, and licensing, see the ModelSim Installation & Licensing Guide. The manual can be downloaded from:

How to Get Support
For information on how to obtain technical support visit a support page at:

Release Notes Archives
For release notes of previous versions visit the release notes archive at:
or find them in the installed modeltech tree in <path to modeltech installation>/docs/rlsnotes


Index to Release Notes
Key Information
User Interface Defects Repaired in 6.0 Beta
Verilog Defects Repaired in 6.0 Beta
PLI Defects Repaired in 6.0 Beta
VHDL Defects Repaired in 6.0 Beta
FLI Defects Repaired in 6.0 Beta
VITAL Defects Repaired in 6.0 Beta
SystemC Defects Repaired in 6.0 Beta
PSL Defects Repaired in 6.0 Beta
Mixed Language Defects Repaired in 6.0 Beta
General Defects Repaired in 6.0 Beta
Mentor Graphics DRs Repaired in 6.0 Beta
Known Defects in 6.0 Beta
Product Changes to 6.0 Beta
New Features Added to 6.0 Beta


Key Information

The following platform changes are effective as of the 6.0 release.

RedHat 6.0 through 7.1 are no longer supported.
Support for AIX will be discontinued in the next release.
You must recompile or refresh your models if you are moving forward from 5.8x or earlier release versions. See "Regenerating your Libraries" in the ModelSim Installation & Licensing Guide for more information on refreshing your models.


User Interface Defects Repaired in 6.0 Beta

Under Windows, if ModelSim is asked to open a file, and the user has a custom tool associated with this file, ModelSim will now check to see if the custom association is actually vsim.exe, vish.exe, or modelsim.exe. This prevents the infinite launch recursion that some customers have experienced.
VHDL access types can now be expanded in the Variables window.


Verilog Defects Repaired in 6.0 Beta


PLI Defects Repaired in 6.0 Beta


VHDL Defects Repaired in 6.0 Beta

When a VHDL entity and architecture are in different source files, and the entity contains executable code, ModelSim is now able to set breakpoints in the entity code and correctly display entity source while stepping through the entity code. The same is true of VHDL code in a PSL vunit, which is necessarily in different source file(s) from the entity and architecture.
Under the following conditions:

Default binding is used,

The component is directly visible,

Two different matching entities are referenced by (different) USE clauses,

One of these entities could be incorrectly chosen for binding.
When a design used the foreign language interface, ModelSim hung and issued a confusing error message if the pathname in the -foreign string contained parentheses.
The predefined attributes 'HIGH and 'LOW return the upper and lower bound, respectively, of a range. The LRM definitions of upper bound and lower bound in section "3.1 Scalar types" are not useful if the range is a null range, and in fact are contradicted by Note 1 in section "14.1 Predefined attributes". ModelSim now implements this Note, not the formal definitions of upper and lower bounds. The implication is that for a non-null range, there is no change in behavior, and LOW <= HIGH as before. For a null range, applying the definition in the Note results in HIGH < LOW and in fact this condition can be used to determine if a range is null.
Using the "NOT" function for pre-defined types like bit, bit_vector, etc. as the actual/formal port of an instance caused vsim to crash.


FLI Defects Repaired in 6.0 Beta


VITAL Defects Repaired in 6.0 Beta


SystemC Defects Repaired in 6.0 Beta

All SystemC kernel messages have been ported to the ModelSim message system. Hence verror can be used to get more detailed information on these errors.


PSL Defects Repaired in 6.0 Beta


Mixed Language Defects Repaired in 6.0 Beta

ModelSim does not allow VHDL generics of type std_logic_vector on the interface from Verilog to VHDL. In previous releases, this restriction was not enforced and the generic value was passed incorrectly. An error is now issued.
If a Verilog module is directly instantiated in VHDL using the 93 direct entity construct, incorrect values could occur if a type conversion or conversion function was used on the actual. The resulting type of the type conversion or conversion function needed to be BIT, BIT_VECTOR, STD_LOGIC, or STD_LOGIC_VECTOR.


General Defects Repaired in 6.0 Beta


Mentor Graphics DRs Repaired in 6.0 Beta


Known Defects in 6.0 Beta

Verilog configurations do not work correctly with the vopt flow. You must use the -fast option on the vlog command line for Verilog configurations to work correctly.


Product Changes to 6.0 Beta

The C Debug tool is now supported in the hpux_ia64 version of ModelSim. The HP wdb/gdb 4.2 debugger is used and packaged with ModelSim.
OEM applications that bind with libvsim on hppa64 must now also include libxnet (i.e. -lxnet) when linking their applicaiton.
The 'raw_data' argument to profile option is no longer needed or supported. Both raw count and percentage values are now reported.
The Pref*(user_hook) will no longer be saved when doing a Save Preferences or [write preferences]. The reason is that the hook will most likely fail unless the associated callback functions are also saved and it is not possible to discover all necessary functions for saving.
Simulation Option changes, accessed from the "Simulation Options" dialog box, are recorded in the active ini file, if the file is writable, and will affect the current session as well as all future sessions. If the file is read-only, the option changes will affect only the current session. The simulation options affected are:
BreakOnAssertion RunLength
DefaultForceKind StdArithNoWarnings
DefaultRadix WLFCompress
IgnoreError WLFDeleteOnQuit
IgnoreFailure WLFOptimize
IgnoreNote WLFSaveAllRegions
IgnoreWarning WLFSizeLimit
IterationLimit WLFTimeLimit


New Features Added to 6.0 Beta

This feature is supported in ModelSim SE only.

A new executable called vopt has been added. It enhances the functionality that was previously obtained by compiling Verilog source files with the -fast or +opt switches.

vopt performs design-wide optimizations, but also allows VHDL design units to be included. It's effectively the same as using vlog +opt, but with support for VHDL as well.

It also generates a new type of library design unit, which shows up as an "OPTIMIZED DESIGN" when a vdir command is executed. You may directly simulate an optimized design by simply invoking vsim directly on it.

vopt works on one or more top-level modules that represent the design root(s). It traverses the entire design, optimizes it, and writes the output to the requested location. For example, if "top" is the root of the design, one might do: "vopt top -o mydesign".

The -o switch is used to specify the output location, in this case "mydesign". You can then simply do "vsim mydesign" to invoke on the optimized design.

vsim also contains provisions for automatically invoking vopt on a design. This is not on by default, but can be enabled by setting the variable VoptFlow to 1 in your modelsim.ini file. See the SE User's Manual for more details on the automatic invocation of vopt.

Note that the vopt step is NOT required and simply exists as a refinement step for the previous functionality implemented with the Verilog compilers' (vlog) -fast and +opt switches.
The GUI can now handle array indices as enumerations.
Additional interface features for SystemVerilog were added:
Export and import tasks and functions in modports are now supported.
When a modport is specified for a module instance, the use of any interface item not listed in that modport will produce an error.
Interface parameters can now be used.
The ModelSim language templates have been extended to include SystemC so that you can have help writing SystemC designs and testbenches using the C++ and SystemC language contructs.
SystemC time resolution and user time unit can now be set using the sc_set_time_resolution() and sc_set_default_time_unit() functions from the SystemC source code. The behavior of these functions remains unchanged from their native OSCI implementation for designs containing only SystemC modules. Please refer to the ModelSim Users Manual for details on the resolution limit and default time unit selection for mixed-language designs.
Modelsim 6.0 contains enhancements to the FLI to support SystemC. In addition to the current acc header files acc_user.h and acc_vhdl.h, there is now a third file called acc_sc.h which contains the constant definitions for the SystemC regions, accScModule, and signals, accScPrimChannel.
All of the FLI functions that return an existing mtiRegionIdT can now return SystemC regions. These functions are:

Enhanced Region Functions
mti_GetRegionKind() called on a SystemC region returns accScModule.
mti_CreateRegion() has not yet been enhanced to support SystemC regions.
All of the FLI functions that return an existing mtiSignalIdT can now return SystemC signals. These functions are:

Enhanced Signal Functions
mti_GetRegionKind() called on a SystemC signal returns accScPrimChannel.
mti_CreateSignal() has not yet been enhanced to support SystemC regions.
Functions that take an mtiRegionIdT or mtiSignalIdT argument which have not yet been enhanced to support SystemC will result in an error message when SystemC arguments are passed to them. These functions are:

Region Functions
mti_CreateRegion() - takes an mtiRegionIdT
Process Functions
mti_Sensitize() - takes an mtiSignalIdT
Signal Functions
mti_CreateSignal() - takes an mtiRegionIdT
mti_ForceSignal() - takes an mtiSignalIdT
mti_ReleaseSignal() - takes an mtiSignalIdT
mti_GetSignalValue() - takes an mtiSignalIdT
mti_GetSignalValueIndirect() - takes an mtiSignalIdT
mti_GetArraySignalValue() - takes an mtiSignalIdT
mti_SetSignalValue() - takes an mtiSignalIdT
mti_SignalIsResolved() - takes an mtiSignalIdT
Driver Functions
mti_CreateDriver() - takes an mtiSignalIdT

The cosimulation interface functions have been similarly updated to support SystemC. For documentation, see cosim.note in the oem directory.
sccom now has a -f option which enables the specification of commands in a file.
An SC signal (including sc_signal, sc_buffer, sc_signal_resolved, and sc_signal_rv) can control or observe an HDL signal using the two new member functions:

bool control_foreign_signal(const char* name);

bool observe_foreign_signal(const char* name);
Controlling an HDL signal from an sc_clock is also supported using control_foreign_signal().
The "extern forkjoin task" feature in SystemVerilog interfaces is now supported.
Message suppression and severity setting can be done on the command line (for vcom, vlog, sccom and vsim). The syntax is:
-note <message number>[,<message number>...]
-warning <message number>[,<message number>...]
-error <message number>[,<message number>...]
-suppress <message number>[,<message number>...]
This can also be done by adding directives to the msg_system section [msg_system] of the modelsim.ini file. The syntax is:
note = <message number>[,<message number>...]
warning = <message number>[,<message number>...]
error = <message number>[,<message number}>...]
suppress = <message number>[,<message number>...]
For -note, -warning, and -error, the listed messages will have their severity set to the level specified by the switch. For -suppress, the listed messages will be suppressed. Note: Internal and fatal messages can't be suppressed nor can they have their severity level changed. The following is an example command line usage of the -suppress switch:
vsim -suppress 3007,3009 mytop
In this example the numbers map to the following messages:
3007 - Defparam iteration limit exceeded.
3009 - Module does not have a `timescale directive in effect, but previous modules do.
VHDL 2002 protected types have been implemented in ModelSim. Because the standard specification is highly contradictory on operators for protected types, the operators have not been implemented.
The $nochange timing check is now supported in optimized cells.
Dynamic arrays may now be used as parameters for tasks, as in:
task sum(input int a[], b[], output int x[]);
The size of a dynamic array parameter is set before the call to the task, so the task sees x in the above example as if it were set with new at the start of the task's code.
On UNIX platforms it is now possible to have ModelSim load PLI and FLI shared objects with global symbol visibility.
Symbols in global shared objects can be referred to by C/C++ code in any other shared object.
You can specify global shared objects in two ways:
Use "vsim -gblso ". Multiple -gblso options can be specified.
Use variable GlobalSharedObjectList in modelsim.ini.
Any global shared objects are loaded prior to all other shared objects in the system. In addition, global shared objects are listed in the order specified by the user.
This feature is not supported on AIX or Windows. You should not specify a SystemVerilog DPI import shared object as global if it calls any DPI export tasks or functions.
ModelSim 6.0 contains support for sparse Verilog memories. Sparse memories yield slower runtime performance than default memories, but much larger storage can be handled when relatively few memory addresses are accessed.
There are two modes of operation:

The first mode is an automatic mode based on the new modelsim.ini variable "SparseMemThreshold". This variable specifies the memory depth above which Verilog memories are automatically implemented with a sparse algorithm. Note that only simple Verilog 2-D reg arrays can be made sparse at this time. For the new vopt flow, the reg arrays must be sized with elaboration-time constants (including paramters). But for the incremental flow, the reg arrays must be sized with compile-time constants (not parameters).

The second mode of operation involves manual specification of sparse memories in source code. There are two ways to specify sparseness: Using Verilog 2001 attributes and using metacomment syntax.

The following are examples of using Verilog 2001 attribute syntax:
(* mti_sparse *) reg [15:0] mymem1 [0:10000000];
(* mti_sparse = 1 *) reg [127:0] mymem2 [0:10000000000];
If you want to turn off automatic sparse mode for a given memory instance, you can use attribute syntax as follows:
(* mti_sparse = 0 *) reg [31:0] mymem3 [0:5000000];

You can use a simple metacomment /*sparse*/ (no whitespace) also:
reg /*sparse*/ [15:0] mymem4 [0:20000];
To find out which memories in your design were successfully identified and implemented as sparse, you can use vsim's write report -l command. This command lists each sparse memory's name and the current amount of byte storage consumed by the memory.

Modelsim 6.0 contains two new command line and one modelsim.ini file option for PSL assume directives. They are as follows.
vsim command line options
-assume : Simulate PSL assume directives same as assert directives.
-noassume : Do not simulate PSL assume directives.
By default, PSL assume directive is simulated as assert directive.
modelsim.ini file variable
SimulateAssumeDirectives = 0 Do not simulate PSL assume directive.
SimulateAssumeDirectives = 1 Simulate PSL assume directive as assert directive.
Default value for SimulateAssumeDirectives = 1
Modelsim 6.0 has support for accessing command line options from within SystemC code.

New vsim command line option for SystemC argc/argv support:
[-sc_arg <string> ...]
Specifies a string representing a startup argument which is subsequently accessible from within SystemC via the sc_argc() and sc_argv() functions.

New functions:
int sc_argc()
const char * const *sc_argv()
These global functions return respectively the number of and the actual arguments specified on the vsim command line with the -sc_arg option. These functions can be invoked from anywhere within SystemC code.
SystemVerilog dynamic memories are now supported in the memtool GUI.
WLF Time Collapsing is a new feature which allows three different modes of recording events to a WLF file. The modes are controlled with a vsim command switch or the WLFCollapseMode modelsim.ini variable. Briefly, the three modes are:
No Collapse: All events for each logged signal are recorded to the WLF file.
Delta Collapse: The final value for a logged signal is recorded at the end of the delta in which the signal has one or more events. (default)
Time Collapse: The final value for a logged signal is recorded at the end of the time step in which the signal has one or more events.
Please see the ModelSim User's Manual for further details.
SystemC debug now includes aggregates of signals and ports. Aggregates may be arrays, structures, or classes where all members are signals or ports. Aggregates that combine other objects such as modules or C/C++ intrinsic data types are not supported in debug, though they remain simulatable.
struct myBus {
sc_signal i;
sc_signal d;

myBus busPair[2];

The example above illustrates an array of structures of signals. This complex aggregate is debuggable and appears in ModelSim as a signal with the type array of structure. The aggregate and its elements may be accessed with the usual C/C++ style syntax:
describe busPair
examine { busPair[0].i }
add wave busPair

Name binding must be enabled for debugging of aggregate signals and ports.
SystemC debug support now includes sc_fifos and ports for fifos. In ModelSim, an sc_fifo appears as an array of type T. All fifos are normalized for display by the examine command or in the GUI windows such that:
The left-most (examine commnd) or top-most (Wave window) element is the next value to be read from the fifo.
Each element is shown.
Empty elements are marked as unused.
The next element that can be written is the left-most or top-most unused element.
SystemC primitive channels like sc_semaphore and sc_mutex are now supported for debug.
Member variables of SystemC modules (SC_MODULE) are now supported for debug.
ModelSim 6.0 supports SystemC on Windows. sccom uses MinGW gcc 3.2.3 for compiling the SystemC source code. C-Debug is supported on Windows with MinGW gdb 6.0.
Parameter passing on SystemC and HDL boundary is now supported.
sccom -work is now supported.
vcom and vsim now support default binding at compile or load time for binding VHDL component instances to their entities. The default in 6.0 is to perform default binding at load time.
Selecting default binding time:
Use vcom -bindAtCompile to perform default binding at compile time. Use vcom -bindAtLoad to perform default binding at load time.
Set the BindAtCompile variable in the modelsim.ini file to 1 to perform default binding at compile time. Leave the variable set to 0 to peform default binding at load time.
Comparison of the two default binding times:
Default binding at compile time provides earlier detection of errors and may sometimes give clearer error messages. However, it requires a bottom-up order of compilation (i.e., an instantiated entity must be compiled before the design unit which instantiates it.) Also, some spurious warning messages may be generated.
Default binding at load time gives more flexibility in the order in which design units are analyzed and does not give unnecessary warning messages.
Expected differences with earlier ModelSim versions:
When you use default binding at load time, fewer design units are loaded during compilation, so the vcom.log file will have fewer "loading" messages.
When you use default binding at load time, the compiler does not check to see if default binding is possible. Therefore, messages such as the following will no longer appear: "** Warning: [1] File1.vhd(532): No default binding for component 'xyz'. (No entity named 'xyz' was found.)"
The PSL 1.1 label feature is now supported.
-- psl mylabel: assert never ( count>limit );
The PSL 1.1 report keyword has been added for PSL directives and appears in the assertion log or transcript.
-- psl assert never ( count>limit ) report "Count over limit." ;
Functional coverage is implemented in ModelSim 6.0 through the PSL cover directive. A functional coverage GUI is available as one of the product's debug windows that offers a browser and various other GUIs. The fcover command line interface is available. There is a chapter of the SE manual that discusses the new features.
Initial source code release of the .../modeltech/verilog_src/verilog_psl_checkers and .../modeltech/vhdl_src/vhdl_psl_checkers libraries.
The SystemVerilog Direct Programming Interface (DPI) is supported in ModelSim 6.0. ModelSim's DPI is compliant with the SystemVerilog 3.1a LRM. There are several limitations in the current release:
Structs and unions cannot be passed as arguments to import or export tasks/functions
Unpacked arrays cannot be passed as arguments to export tasks/functions
Open arrays are not supported
Import/export task/function arguments with parameterized types are supported only in the vopt flow
If DPI tasks/functions are present in a design, checkpoint save is not supported
If DPI tasks/functions are present in a design, restart from time 0 is not supported
The rs6000 and rs64 platforms are not supported in the 6.0Beta1 release
Please see the ModelSim 6.0 User's Guide for more details on using DPI on your platform of choice.
New SystemVerilog features:
Integer/logic & real literals
logic data type
Real and shortreal data types
Void data types
Classes, partial support
Type casting
Array querying functions
Associative arrays & array methods
Assignment operators
Operations on logic and bit types
Wild equality and wild inequality
do while loop
Jump statements
always_comb always_latch & always_ff
void functions
Class Objects, Object properties and methods, Constuctors
Classes This
Relaxed port connection rules
Time unit & precision
Interface modports
Tasks and functions in interfaces
Parameterized interfaces
Direct programming interface (see release note 50)

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