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Similar to Leo_o2 I have heard from some experts in RC-MOS clamps that it is not so easy to implement this protection type in High voltage technology but it could be due to a lack of experience in HV.
But using a snapback (gg)NMOS for HV technologies is really problematic. I have worked with number (10+: 0.7um --> 0.15um) of HV process technologies in the past and in 90% of the cases the NMOS device does not survive snapback operation beyond the first 10ns-20ns. In the remaining 10% the NMOS could be driven into snapback but was still very weak during ESD.
SCR's are certainly used in high voltage for ESD protection. But do watch-out for the low holding voltage. If you are designing in severe or 'harsh' environment like automotive signal or supply noise could trigger the SCR, leading to latch-up. Many in the automotive world still rely on (big size) zener diodes for protection.
Thank u
for 10~15V cmos process ,shall I use two 5v stacked gate-source-nwell-connected pmos ? It can survive 20v on common operation. when positive to VSS ESD, two pn junction breakdown , both pn junction operates 8v-10v holding voltage .
Is it possible? It's my imagin.
It seems to be a reasonable approach to use a stack of 2 5V PMOS devices. Do you have silicon data from a single PMOS and from the combination circuit?
When the PN junctions go into breakdown, it will also trigger PNP action. This should be better than just a series connection of the single diodes.
You mentioned 8-10V drop over a single PMOS. Can the parallel sensitive circuit survive >20V during the entire ESD stress pulse? Do you have an idea about the maximum voltage for this circuit?
What is it : GCNMOS?
We use 40V HV process and use SCR only for special pins for which external voltage can exceed Vcc or can be lower GND. For the rest of HV pins we don't use SCR.
HBM is 4KV. The fact is that HV transistor gate oxide is 1200A. So they can withstand much higer voltage.
I has not the data of 5v pmos TLP test . usually the protected device for 0.35um 5v/16V cmos process , 16v gate-oxide breakdown is 20+ V .
two 5v protecting pmos 's area is large , also I have no chance to verify .
I has seen a paper which present two or three stacked FOD device pass 2000V HBM for vdd-vss ESD protecting circuit.
If the PMOS series connection takes too much area you might consider SCR based approach. Those are typically smaller in size. Many SCR types exist but most are patented so you'd better get a verified solution so that you don't risk infringement.
However you must also understand the consequences related to latch-up for instance. The holding voltage of the SCR is certainly below the 16V. This means that it will create latch-up if the device is triggered into low ohmic state during biased conditions.
Design techniques exist to prevent unwanted triggering. These include higher trigger voltage and trigger current and increased holding current level. Also an externally placed (large = uF) capacitor between Vdd and Vss can ensure that the trigger point is never reached in real application.
Regarding tolerating latch-up you might use a kind of formula: P1 x C1
P1 = What is the probability that the IC is is biased beyond the standard conditions tested for in qualification. For instance, an automotive environment is called 'harsh' partly because it is hard to predict the real transient voltage, currents applied at the IC.
C1 = The cost associated with a latch-up occurance. For instance, if latch-up would bring a human body in danger (e.g. ABS system in a car) then I propose you should look into another solution.
I hope this somehow makes sense to you. Let me know if you need further help.
I think stacked PMOS might not be effective. As I know, It is much more difficult to trigger parasite PNP into snap-back than NPN. That's the reason why NMOS is commonly employed as ESD protection instead of PMOS. If possible, stacked NMOS will be much better. Of course, the max voltage stress must be checked. Another point is Deep Nwell should be connected to the drain (PAD) if isolated NMOS is placed at the high side. Of course the structure can be simplified to save area and still remain NPN discharging path. And it can be changed to SCR to some extent too. It will be more effective.
Leo_o2 is right that in most cases NMOS (NPN) based ESD protection is better than PMOS (PNP) based protection. The voltage drop during ESD will be much lower with NPN solution.
However, shrbht is talking about a 16V application. To my knowledge the HV-NMOS/NPN device is not effective for ESD protection in this kind of technology: The NPN cannot survive snapback. Moreover, it has a deep snapback just before failure which may lead to latch-up.
I have seen application with effective protection using stacked PMOS in 16V technology.
you have seen stacked pmos in 16V process?
I miss the chance that invent the ESD protecting structre.
but I worry about the pmos 's gate-oxide !
thank u
I'm sorry for my late answer.Yes I have seen stacked LV PMOS to work in HV techology. Gate oxide reliability strongly depends on the application details and gate connections. If the 16V is present on the pin all the time it may cause reliability degradation at the gate. But if this is the only issue then you may take out the gate completely and use stacked PNP structures instead?
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