Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

why unit sized cap is always square

Status
Not open for further replies.

Santosh.K

Newbie level 3
Joined
Jan 4, 2011
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,299
Hi can any one explain why unit sized cap is always square.
Thanks in advance.
 

Intresting, but i am not sure what you mean actually? what is a unit sized capacitor?
 

In cmos process the capacitors which are used of some unit sizes depending on technology are called unit sized caps.
 

Squares pack nicely, and square maximizes (within ortho
geometry anyway) the desired areal capacitance against
the undesired periphery / fringe capacitance.
 

Thanks,,,
Does it add on to the error calculation like the ratio of perimeter to area...???
 

In fact, you don't need to have square cap always. In many conmercial chips, other shape is used for unit-cap.
 

According to matching theory, you should keep perimeter comparing to area the more smaller it is, the better matching it is.
 

probably, easy to manufacture. lower chance to get it wrong.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top