why this timing report(ISE) says there are Levels of Logic

[rogeret]

questions of timing report(ISE) about logic levels/tas

Hi ,
Could you help me?
The following timing path report is extracted from the final timing report after PAR. My expected period of clock is 4 ns. My target device is xc7v585t-3-ffg1157 (Virtex 7 family).
1.
I cannot understand why the following timing report tells me there are TWO levels of logic in this timing path.
The delay type in this path is sequentially presented : Tshcko -> net -> Tdspdo_B_P_MULT -> net -> Tas.
In my opinion, there is only ONE level of logic because I can see only one logic---DSP48.
Does the delay tpye----tas imply one level of logic? I dont think so because tas is similiar to setup time which is definitely not logic delay.


Here(https://www.xilinx.com/support/documentation/user_guides/ug364.pdf) is the meaning of tas:

At time [B][U]TAS [/U][/B]before clock event 1, the address (2) becomes valid at the A/B/C/D inputs of the RAM

.
2.
Why does tas here have a negative value?
3.
Considering that there is no explicit RAM in my RTL design, why ，after I disable the option of "RAM　EXTRACTION" to extinct logic implemented by RAM，does the delay----tas still exist? In my opinion , tas delay type is related to RAM and delay of tas type imply the existence of RAM, so I cannot understand the reason for the existence of tas delay type (= RAM) considering no explicit RAM in RTL and the disabled "RAM　EXTRACTION" option.

Timing report:

1. --------------------------------------------------------------------------------
3. Paths for end point bx6/r_yw1_6 (SLICE_X63Y327.C5), 1 path
4. --------------------------------------------------------------------------------
5. Slack (setup path): -0.463ns (requirement - (data path - clock path skew + uncertainty))
6. Source: t_nextb/b11_0_1 (FF)
7. Destination: bx6/r_yw1_6 (FF)
8. Requirement: 4.000ns
9. Data Path Delay: 4.388ns (Levels of Logic = 2)
10. Clock Path Skew: -0.040ns (0.975 - 1.015)
11. Source Clock: clk_BUFGP rising at 0.000ns
12. Destination Clock: clk_BUFGP rising at 4.000ns
13. Clock Uncertainty: 0.035ns
15. Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
16. Total System Jitter (TSJ): 0.070ns
17. Total Input Jitter (TIJ): 0.000ns
18. Discrete Jitter (DJ): 0.000ns
19. Phase Error (PE): 0.000ns
21. Maximum Data Path at Slow Process Corner: t_nextb/b11_0_1 to bx6/r_yw1_6
22. Location Delay type Delay(ns) Physical Resource Logical Resource(s)
23. ------------------------------------------------- -------------------
24. SLICE_X62Y251.DMUX Tshcko 0.315 reset_IBUF_589 t_nextb/b11_0_1
25. DSP48_X2Y131.B0 net (fanout=4) 1.391 t_nextb/b11_0_1
26. DSP48_X2Y131.P6 Tdspdo_B_P_MULT 2.280 bx6/Mmult_yw1x bx6/Mmult_yw1x
27. SLICE_X63Y327.C5 net (fanout=1) 0.406 bx6/yw1x<6>
28. SLICE_X63Y327.CLK Tas -0.004 bx6/r_yw1<8>
29. bx6/yw1x<6>_rt
30. bx6/r_yw1_6
31. ------------------------------------------------- ---------------------------
32. Total 4.388ns (2.591ns logic, 1.797ns route)
33. (59.0% logic, 41.0% route)

 

[ads_ee]

Re: questions of timing report(ISE) about logic levels/tas

1.
I cannot understand why the following timing report tells me there are TWO levels of logic in this timing path.

There is only one level the SLICE_X63Y327 probably contains an output register. You should generate a post mapped schematic to look at the implementation details.

2.
Why does tas here have a negative value?

This would just mean the register has a negative setup time, i.e. the clock can arrive before the data.

3.
Considering that there is no explicit RAM in my RTL design, why ，after I disable the option of "RAM　EXTRACTION" to extinct logic implemented by RAM，does the delay----tas still exist? In my opinion , tas delay type is related to RAM and delay of tas type imply the existence of RAM, so I cannot understand the reason for the existence of tas delay type (= RAM) considering no explicit RAM in RTL and the disabled "RAM　EXTRACTION" option.

Tas is a setup time for the A/B/C/D inputs of a slice. It is used for both inputs to a flip flop or for the address input to a LUT RAM.

 

[rogeret]

Re: questions of timing report(ISE) about logic levels/tas

Hi ads_ee ,

Thanks!

This would just mean the register has a negative setup time, i.e. the clock can arrive before the data.

But it is still hard to imagine the existence of a register with a negative setup time. A negative setup time may not accord with the theory of digital circuit.

 

[ads_ee]

I was going to go into details and draw a picture, but got smart and did a search instead. ;-)

Here is a nice explanation...
https://digitalelectronics.blogspot.com/2005/12/negative-setup-and-hold-time.html

and another from the ASIC forum...
https://www.edaboard.com/threads/133490/


Hope that helps with your understanding.

 

[permute]

and if you want a picture:
https://cdstahl.org/?attachment_id=41

as for the extra level of logic, I'm guessing there is something in your code that ends up inferring an extra level, or that the tools have chosen to use a logic element for routing for some reason. in this case, I'm assuming the DMUX muxes in on path for reset and one for non-reset.

 

[rogeret]

I'm guessing there is something in your code that ends up inferring an extra level, or that the tools have chosen to use a logic element for routing for some reason.

Maybe, this is a possible explanation.

in this case, I'm assuming the DMUX muxes in on path for reset and one for non-reset.

But , I dont think it is like this in this case.
In the following timing path, there is still a SLICE_X62Y251.DMUX at the beginning of the path which has only ONE logic level.
Where the difference btw the 2 paths locates at is the SLICE_X63Y327.CLK with delay type of Tdick at the end of this path.
SO , I suspect that why the above timing path has TWO logic levels is that it has SLICE_X63Y327.CLK with delay type of Tas at the end of its path.

Paths for end point bx6/r_yw1_7 (SLICE_X63Y327.DX), 1 path
--------------------------------------------------------------------------------
Slack (setup path): -0.444ns (requirement - (data path - clock path skew + uncertainty))
Source: t_nextb/b11_0_1 (FF)
Destination: bx6/r_yw1_7 (FF)
Requirement: 4.000ns
Data Path Delay: 4.369ns (Levels of Logic = 1)
Clock Path Skew: -0.040ns (0.975 - 1.015)
Source Clock: clk_BUFGP rising at 0.000ns
Destination Clock: clk_BUFGP rising at 4.000ns
Clock Uncertainty: 0.035ns

Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns

Maximum Data Path at Slow Process Corner: t_nextb/b11_0_1 to bx6/r_yw1_7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X62Y251.DMUX Tshcko 0.315 reset_IBUF_589
t_nextb/b11_0_1
DSP48_X2Y131.B0 net (fanout=4) 1.391 t_nextb/b11_0_1
DSP48_X2Y131.P7 Tdspdo_B_P_MULT 2.280 bx6/Mmult_yw1x
bx6/Mmult_yw1x
SLICE_X63Y327.DX net (fanout=1) 0.371 bx6/yw1x<7>
SLICE_X63Y327.CLK Tdick 0.012 bx6/r_yw1<8>
bx6/r_yw1_7
------------------------------------------------- ---------------------------
Total 4.369ns (2.607ns logic, 1.762ns route)
(59.7% logic, 40.3% route)