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why this Gate Count difference

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eda_wiz

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hi,
When I synthesis the same rtl code for different asic libraries in leornad0. I am getting different gate counts. Does anyone knows why is this.

tnx
 

linuxluo

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Hi,
The gate number you mean is how to calculate? But you can ensure that if you use different foundry lib, the result should be different because the cell lib provide is different.
 

eda_wiz

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hi,

HDL is sysnthezised to gatelevel netlist by the tool . We are using different
foundry libraries so that it can be fabricated with different Process technologies. But can the gate count really change ?? :)

Please correct me If i am wrong

tnx
 

sandusty

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Compare those two libraries you will know the results should be different. All gates' timing, area... are different and you don't know how the synthesis tools solve the bag-packing problem...
 

maniasonic

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hi, components in library is vendor dependent, so is the synthesis result.
 

ymli

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different libraries may include different components, ex,
in Library A: NAND2 is included
in Library B: NAND2 is not included
in your design you may use a lot of NAND2 gate, when this NAND2 gates are mapped to target library,
for Library A: synthesizer just use the NAND2 gate;
for Library B: synthesizer may use NAND3/NAND4 to implement NAND2 in your design.
When calculate the gate count, now you get different results.

Good LUCK
 

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