# why the signal register use its previous value?

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#### fahim1

##### Member level 4
according to the following code and test bench at each rising edge of the clock the signal registers value should participate in the calculation but it doesnt happen:
for example ;
at the red circle when x is 5 and signal reg is (5,0,0) the out put should be y=20 (y=x +shl (reg(2)))
but here it calculate the y with the previous values of reg which is (0,0,0) and i dont know why??
i would appreciate if some body help me?

---------main program------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_unsigned.all;
-----------------------------------------
entity fir3 is

port( x : in std_logic_vector (3 downto 0);
clk,rst : in std_logic;
y : out std_logic_vector (7 downto 0));
end fir3;
------------------------------------
architecture fir3_arch of fir3 is
type registers is array (2 downto 0) of std_logic_vector(6 downto 0);
type coefficients is array (3 downto 0) of std_logic_vector(3 downto 0);
signal reg : registers := ("0000000","0000000","0000000");
constant coef : coefficients := ("0001","0010","0011","0100");
-----------------------------------
begin
process(clk,rst)
variable acc,prod : std_logic_vector (7 downto 0) := (others => '0');
variable temp : std_logic_vector (6 downto 0) := (others => '0');
begin
-----------------reset--------------------
if rst='1' then
for i in 2 downto 0 loop
for j in 6 downto 0 loop
reg(i)(j) <= '0';
end loop;
end loop;
-------------register inference + MAC -----------
elsif (clk'event and clk='1') then
acc := (others => '0');
acc := "0000" & x ; --because c0=1 we dont have to multiply
temp := "000" & x ;
prod := ((reg(2)(5 downto 0))& '0') +((reg(1)+reg(1)(5 downto 0))&'0') +((reg(0)(4 downto 0))&"00");
acc := acc + prod ;
reg <= temp & reg(2 downto 1 );
end if;
y <= acc;
end process;
end fir3_arch;
-----------------------------test bench---------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;

ENTITY fir3_testbench IS
END fir3_testbench;

ARCHITECTURE fir3_testbench_arch OF fir3_testbench IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fir3
PORT(
x : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
rst : IN std_logic;
y : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;

--Inputs
signal x : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal rst : std_logic := '0';

--Outputs
signal y : std_logic_vector(7 downto 0);

-- Clock period definitions
constant clk_period : time := 11 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: fir3 PORT MAP (
x => x,
clk => clk,
rst => rst,
y => y
);

-- Clock process definitions
clk_process rocess
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

x <= "0000",
"0101" after 11 ns,
"1010" after 22 ns,
"1111" after 33 ns,
"0000" after 44 ns;

END fir3_testbench_arch;

#### K-J

according to the following code and test bench at each rising edge of the clock the signal registers value should participate in the calculation but it doesnt happen:
for example ;
at the red circle when x is 5 and signal reg is (5,0,0) the out put should be y=20 (y=x +shl (reg(2)))
but here it calculate the y with the previous values of reg which is (0,0,0) and i dont know why??
Because at the rising edge of the clock, the value of reg is (0,0,0) so that is the value that gets used to perform the calculation. After the rising edge, reg is updated to (5,0,0) but there are no more calculations to be performed until the next rising edge occurs.

Kevin Jennings

#### fahim1

##### Member level 4
Because at the rising edge of the clock, the value of reg is (0,0,0) so that is the value that gets used to perform the calculation. After the rising edge, reg is updated to (5,0,0) but there are no more calculations to be performed until the next rising edge occurs.

Kevin Jennings

i have another program with the same situation with x,reg,... but the output is different
i just use multiply instead of the shift i used in first code.
all the parts are the same but the output is different

-----------main code-------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all; --package needed for signed
--use IEEE.NUMERIC_STD.all;
use IEEE.std_logic_unsigned.all;
-----------------------------------------
entity fir2 is
--generic (n :integer :=4; --number of coefficients
--m :integer :=4); --number of bits represent coefficients
port( x : in std_logic_vector (3 downto 0);
clk,rst : in std_logic;
y : out std_logic_vector (7 downto 0));
end fir2;
------------------------------------
architecture fir2_arch of fir2 is
type registers is array (2 downto 0) of std_logic_vector(3 downto 0);
type coefficients is array (3 downto 0) of std_logic_vector(3 downto 0);
signal reg : registers := ("0000","0000","0000");
constant coef : coefficients := ("0001","0010","0011","0100");
-----------------------------------
begin
process(clk,rst)
variable acc,prod : std_logic_vector (7 downto 0) := (others => '0');
begin
-----------------reset--------------------
if rst='1' then
for i in 2 downto 0 loop
for j in 3 downto 0 loop
reg(i)(j) <= '0';
end loop;
end loop;
-------------register inference + MAC -----------
elsif (clk'event and clk='1') then
acc := (others => '0');
acc := coef(0)*x ;
prod := coef(1)*reg(2)+coef(2)*reg(1)+coef(3)*reg(0);
acc := acc + prod ;
reg <= x & reg(2 downto 1 );
end if;
y <= acc;
end process;
end fir2_arch;

#### FvM

##### Super Moderator
Staff member
You just confused the coefficient order. Rather than having c(0) = 1 as assumed in the first code, you have actually c(0) = 4. And so on.

By the way. Why in 2015 people are still starting VHDL with the non-standard Synopsys library std_logic_unsigned?

##### Super Moderator
Staff member
By the way. Why in 2015 people are still starting VHDL with the non-standard Synopsys library std_logic_unsigned?
In all the years I've been going to various training classes in VHDL/Verilog/SystemVerilog presented by numerous companies that specialize in training in those languages, I have never met someone from academia. I've only ever seen those with a few years experience or industry veterans picking up another hardware language or brushing up on the latest revision of the language. Given that most all the VHDL books on the market still have std_logic_unsigned in all their example code that would mean that those in academia would likely be using (or writing) books that use those non-standard Synopsys libraries. I wonder how many of them actually have the latest LRM and have read it.

#### fahim1

##### Member level 4
In all the years I've been going to various training classes in VHDL/Verilog/SystemVerilog presented by numerous companies that specialize in training in those languages, I have never met someone from academia. I've only ever seen those with a few years experience or industry veterans picking up another hardware language or brushing up on the latest revision of the language. Given that most all the VHDL books on the market still have std_logic_unsigned in all their example code that would mean that those in academia would likely be using (or writing) books that use those non-standard Synopsys libraries. I wonder how many of them actually have the latest LRM and have read it.

hi
I am actually a academia.I learned vhdl from books like circuit vhdl design by pedroni.I didnt get completely what u mean.I would appreciate if you explain more and guide me what to do ?
thanks

#### fahim1

##### Member level 4
You just confused the coefficient order. Rather than having c(0) = 1 as assumed in the first code, you have actually c(0) = 4. And so on.

By the way. Why in 2015 people are still starting VHDL with the non-standard Synopsys library std_logic_unsigned?

but I didnt get what u mean,would u explain more please,i didnt change the coefficient orders in my code,its constant.

##### Super Moderator
Staff member
I was just say that I've noticed that using antiquated textbooks without actually reading the LRM keeps the academia side stuck in the VHDL dark ages, teaching the next generation the OLD way to do it. I'm sure there are some that take the time to learn the latest changes in the language and teach the language using the latest LRM (pointing out what tool vendors support or don't support well), but if the questions and code that are posted on this board (from all over the world) are any indication that is more of an exception than the norm.

I just took a look at my Perdoni book and the first mention of the std_logic_unsigned etc packages makes no mention of them being non-standard Synopsys written packages. The acknowledgement they are non-standard shows up some 33 pages later. The only mention that they were from Synopsys comes in the Appendix with no mention that they were introduced by Synopsys as part of their VHDL simulator way back in the late 80's early 90's. Other simulator vendors copied the packages making it an unfortunate de facto standard. As I recall from history the problem stems from Synopsys deciding to compile the library for their arithmetic and signed/unsigned std_logic_vector packages into the IEEE library and then name it something that sounded "official" (who knows that might have been their intention all along). Now everyone excluding those that actually have read the LRM or have at least taken a good look at it or a book that describes which packages are official IEEE VHDL packages, thinks that std_logic_arith, std_logic_unsigned, and std_logic_signed are official IEEE standard (std) packages, even though when you open one of them up it says it's copyright by Synopsys.

- - - Updated - - -

I think FvM is referring to this:
Code:
[FONT=Courier New]constant coef : coefficients := ("0001","0010","0011","0100");
^      ^      ^      ^
index =  3      2      1      0[/FONT]
This is because you defined the array as (3 downto 0) instead of (0 to 3).

fahim1

### fahim1

Points: 2

#### vGoodtimes

std_logic_unsigned gives VHDL's std_logic_vectors an style that is more similar to Verilog. I suspect that is a large part of why SLU has remained.

IEEE has released numeric_std_unsigned, which is the IEEE approved version of std_logic_unsigned. This adds a level of irony because now the "old" way of doing things can be the "new" way just by changing a declaration.

numeric_std and numeric_std_unsigned do play a role in the actual logic. These can appear in corner cases such as comparing vectors of different lengths. The normal "=" will provide a useful warning and return false. NSU's "=" will convert the arguments to unsigned values and perform the comparison.

fahim1

Points: 2