#### fahim1

##### Member level 4

for example ;

at the red circle when x is 5 and signal reg is (5,0,0) the out put should be y=20 (y=x +shl (reg(2)))

but here it calculate the y with the previous values of reg which is (0,0,0) and i dont know why??

i would appreciate if some body help me?

---------main program------------

-----------------------------test bench---------------------library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.all;

use IEEE.std_logic_unsigned.all;

-----------------------------------------

entity fir3 is

port( x : in std_logic_vector (3 downto 0);

clk,rst : in std_logic;

y : out std_logic_vector (7 downto 0));

end fir3;

------------------------------------

architecture fir3_arch of fir3 is

type registers is array (2 downto 0) of std_logic_vector(6 downto 0);

type coefficients is array (3 downto 0) of std_logic_vector(3 downto 0);

signal reg : registers := ("0000000","0000000","0000000");

constant coef : coefficients := ("0001","0010","0011","0100");

-----------------------------------

begin

process(clk,rst)

variable acc,prod : std_logic_vector (7 downto 0) := (others => '0');

variable temp : std_logic_vector (6 downto 0) := (others => '0');

begin

-----------------reset--------------------

if rst='1' then

for i in 2 downto 0 loop

for j in 6 downto 0 loop

reg(i)(j) <= '0';

end loop;

end loop;

-------------register inference + MAC -----------

elsif (clk'event and clk='1') then

acc := (others => '0');

acc := "0000" & x ; --because c0=1 we dont have to multiply

temp := "000" & x ;

prod := ((reg(2)(5 downto 0))& '0') +((reg(1)+reg(1)(5 downto 0))&'0') +((reg(0)(4 downto 0))&"00");

acc := acc + prod ;

reg <= temp & reg(2 downto 1 );

end if;

y <= acc;

end process;

end fir3_arch;

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

use IEEE.std_logic_unsigned.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

USE ieee.numeric_std.ALL;

ENTITY fir3_testbench IS

END fir3_testbench;

ARCHITECTURE fir3_testbench_arch OF fir3_testbench IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT fir3

PORT(

x : IN std_logic_vector(3 downto 0);

clk : IN std_logic;

rst : IN std_logic;

y : OUT std_logic_vector(7 downto 0)

);

END COMPONENT;

--Inputs

signal x : std_logic_vector(3 downto 0) := (others => '0');

signal clk : std_logic := '0';

signal rst : std_logic := '0';

--Outputs

signal y : std_logic_vector(7 downto 0);

-- Clock period definitions

constant clk_period : time := 11 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: fir3 PORT MAP (

x => x,

clk => clk,

rst => rst,

y => y

);

-- Clock process definitions

clk_process rocess

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

end process;

x <= "0000",

"0101" after 11 ns,

"1010" after 22 ns,

"1111" after 33 ns,

"0000" after 44 ns;

END fir3_testbench_arch;