clould365
Newbie level 4
There are two different expression
1.reg baud_rate=3;
wire [15:0] one_bit_clock_nums;
assign one_bit_clock_nums =2083/(2^baud_rate);
2.assign one_bit_clock_nums =2083/8;
In ModelSim,
the result are
1.2083
2.260
what's the reason?
BTW,Is division Synthesizable?
1.reg baud_rate=3;
wire [15:0] one_bit_clock_nums;
assign one_bit_clock_nums =2083/(2^baud_rate);
2.assign one_bit_clock_nums =2083/8;
In ModelSim,
the result are
1.2083
2.260
what's the reason?
BTW,Is division Synthesizable?