stackprogramer
Full Member level 3
Why does the a=a+b expression that works in CPP not work the same CPP in Verilog???
when I used a=a+b; the expression, the last value of a reg is not summed with b, the result return b not a+b in Verilog...
How can implement a=a+b with at least resource in FPGA
Thanks in advance
when I used a=a+b; the expression, the last value of a reg is not summed with b, the result return b not a+b in Verilog...
How can implement a=a+b with at least resource in FPGA
Thanks in advance