Set-up time and hold time are the constraints from the process itself ..so this is wrong to say why they are needed. they are always there..? Only yours data should meet these constraints with respect to the trigerring signal(clk).
Requirement for set-up time: Input node takes some time to charge ( parasitic capacitance or oxide capacitance+ parasitic capacitance.so it is required to get the exact voltage at the node .
Requirement for hold time: since transistor takes finite time in triggering , so when u trigger urs transitor with respect to clk , this is time required to hold the incoming data stable till the triggers does not propagate. otherwise u will sample wrong data.
--pyare