Why setup time is needed?????????

[nitin_ndg]

Hi
what is the theory behind the setup and hold time requirment for FF.

nitin

 

[A.Anand Srinivasan]

the reason behind setup time and hold time is the time required for the input transistors to respond to the particular signal.... it involves charging of capacitors and switching of the transistor.....

 

[nitin_ndg]

Thanks
That is ok ....... capecitor needs to be charged for particular value to respond as ONE.

then
1.Why HOLD time required???
2. Why Th is more concered then Tsu.

and even circuit can respond if setup time failuer but hold time is meeting.

 

[A.Anand Srinivasan]

actually setup time constraint induces metastability so the right output might be obtained.... it is not so for hold time because you are discharging or charging the capacitance while it is supposed to be the other way around and this would surely lead to a error...

 

[swapnil_vlsi]

setuptime
It is ,the min length of time that a data i/p is stable before the active clock transition.
Hold time
It is ,the min length of time that a data i/p is stable after the active clock transition.

 

[nitin_ndg]

Hi Swapnil_vlsi what u told is defination of setup and hold time.

my question is theory behind Tsu and Th.

Tsu needs to charch the cepacitor ..
next Q. is why Th is requored...

 

[FrankCh]

You miss the basics of timing, which is prehibitive for IC designers.

 

[nitin_ndg]

What ? i didn't get

 

[avimit]

needed? what do you mean? there is no 'need' for setup and hold time. Unfortunately they are there. NO body has put setup and hold time in the FF as a need.
Kr,
Avi
https://www.vlsiip.com

 

[nitin_ndg]

Hi avimit

Needed ??? meas....there is a perameter Tsu. this time relation has to be maintain with respect to clk....

Can any one tell me what is theory behind hold time..

thanks

 

[JFrensch]

put it this way:
if you want to drive your car into a garage, the gate should be open
'before' you enter (=> setup) and should close 'after' you have entered
(hold).

If the input to a FF violates it's hold time, the FF might not be able to decide whether it should store the 'old' or the 'new' value

 

[nitin_ndg]

Hi, thanks JFrensch
what about setup time voilation??????

 

[pmsarkar]

Set-up time and hold time are the constraints from the process itself ..so this is wrong to say why they are needed. they are always there..? Only yours data should meet these constraints with respect to the trigerring signal(clk).

Requirement for set-up time: Input node takes some time to charge ( parasitic capacitance or oxide capacitance+ parasitic capacitance.so it is required to get the exact voltage at the node .

Requirement for hold time: since transistor takes finite time in triggering , so when u trigger urs transitor with respect to clk , this is time required to hold the incoming data stable till the triggers does not propagate. otherwise u will sample wrong data.

--pyare

 

[kannanunni]

Hi Swapnil_vlsi what u told is defination of setup and hold time.

my question is theory behind Tsu and Th.

Tsu needs to charch the cepacitor ..
next Q. is why Th is requored...

Flip-flops are bistable devices. However to switch the state you need to drive the gate for a finite time. If your input is short, the output will revert back to the original state. Thus we need hold time to successfully switch the state. for setup time, After you apply the input signal it takes some time to charge/discharge the input capacitors. Before that the input nodes will have wrong voltages. Thus set-up time is required to fully prepare the input for sampling...