Why rise/pos edge flops are preferred over neg edge flops

[curty]

My query why we always prefer pos edge flops over neg edge ..
In a design having only pos edge flops if we replace those with neg edge flops ..
All the flop to flop paths would be single cycle , timing wise there is no impact.
But what is impact over power & area with this approach ?

 

[curty]

Also if we use neg edge flops. In sleep mode they will get 1 instead of zero. That could be one reason for not using these flops .. What say ?

 

[rca]

1- there is no specific reason to used a design purely with rising edge instead falling edge.
Some designer used both for timing clock ration issue, other one have 50% of both to have less voltage drop around the clock edge.
2- I don't know where you see you will get a 1 instead a zero in sleep mode? Only the reset/set pins could determine the q value, no?

 

[englishdogg]

I think the impact of this choice is usuallly on DFT. (i learnt this part from this forum itself)
Depending on the clk waveform (0->1->0), then negedge should be first. If your clock is (1->0->1), then posedge should be first. The reason is because you don't want a scan data to hop across 2 flip-flops with a single clock pulse, which means those 2 flip-flops will always end up with the same scan-in data.
For example, if your clock is 0->1->0 and your chain is as follows:
ScanIn -> FF1(pos) -> FF2(neg) -> ScanOut
whatever we put into ScanIn will appear at ScanOut after a single pulse. However,
ScanIn -> FF1(neg) -> FF2(pos) -> ScanOut
then the posedge clock will update FF2 (using data stored in FF1), then afterwards the negedge will update FF1 (using ScanIn).

 

[curty]

RCA you are right there is no specific reason. But still we prefer pos edge flops. You area talking about actual scenario when we have a mix of pos & neg edge flops.
But i am talking about hypothetical case, where design is having only pos edge flops. If we ignore the interface timing, we can replace all pos edge with neg edge flops ..
So what would be the implications, then ?

In sleep mode when we turn of clock to some module through ICGs then clk pin of neg edge flops will get 1 instead of zero.
If we have all the negedge flops in design, i guess dft wouldn't have any issue as scan paths will be single clock cycle ...

 

[rca]

You could have the clock to low value when the chip is in sleep mode, that is really dependent of you.

 

[curty]

That right, but for neg edge flops we have to use 1@clk pin for sleep mode ... .. Zero will be used only when block is power gated & its in off state ..