Re: asychronous fio design
because read clock and write clock are asynchronous,
write address is generated in write clock domain,
read address is generated in read clock domain. in asyn fifio,
we need to compare write address and read address to
determine empty and full flag as well as how many bytes
are in fifo. so we must pass write address to read clock domain
and pass read address to write clock domain.
if read address and write address is not encoded in gray code,
address will has many bits to change, that will lead
wrong address. because we can't pass multi-bits data
across asynchronous boundary reliablely.
by using gray code, this problem is solved.
best regards
dak-ju said:
I want to know why in the asynchronous fifo design , the read and the write pointer is gray encoded?