why posedge and negedge can be used to detect the edge of clock, but CAN'T others?

[zsuhh]

For example, it can not be used for Key press rise/fall edge detect, but why it can be used for clock or reset? Thank you!

 

[FvM]

You are asking about Verilog hardware description language. A clock edge sensitive always block describes e.g. a flip-flop in hardware. So your question can be translated like "can we (or better should we) use a flip-flop clock input for key press detection".

Basically you can, but the idea involves some problems like key bounce. A key signal feeding a flip-flop clock input can be occasionally found in discrete logic design, usually supplemented by RC signal conditioning circuits that are necessary to make it work at all. In synchronous programmable logic designs, these signal conditioning means can't be applied and there are much better ways to detect the rising or falling edge of a slow external signal.

 

[ThisIsNotSam]

For example, it can not be used for Key press rise/fall edge detect, but why it can be used for clock or reset? Thank you!

many reasons. for the clock, there will always be a clock tree behind it. this guarantees certain characteristics to the clock signal that make it feasible to design digital logic the way we do. with external signals there are no such guaranties.