Why PLL phase margin degrades when you change the input frequency?

[surianova]

hi all!

I have a question to ask regarding PLL. I found out that as i change the input frequency, the phase margin degrade... but from the PLL transfer function, it shd be independent of input frequency, rite?

i put input frequency 60 MHz, the loop filter stable..no ringing

when i put lower input frequency to 40 MHz, the loop filter voltage start to ring and take long time to lock.

when i put input frequency 30 MHz, the loop filter voltage start to ocsilate.

As we can as i lower the input frequency, the phase margin degrade and cause ocsilation..


anyone experince this before or any theory to explain this . thanks

 

[hackjiang]

Re: PLL phase margin

Please post the structure diagram of your loop.

 

[eeliuliu]

PLL phase margin

how about thetuning range of your VCO?
is there any change of your KVCO when doing these ?

 

[surianova]

Re: PLL phase margin

how about thetuning range of your VCO?
is there any change of your KVCO when doing these ?

yes, my vco gain do vary.. but i already simulate with Matlab which show phase margin still in the range of 45 to 50 degree with the vco gain variation. But one thing now suspect is may be the loop bandwidth too high, the loop bandwidth is 1 MHz. And the input frequency that give problem is 30 Mhz...any idea if the input frequency is 30 MHz, what is the max loop bandwidth can go? Will it cause problem with input frequency 30 MHz with the loop bandwidth 1 MHz? Thanks for your opinion.

 

[surianova]

Re: PLL phase margin

how about thetuning range of your VCO?
is there any change of your KVCO when doing these ?

yes, my vco gain do vary.. but i already simulate with Matlab which show phase margin still in the range of 45 to 50 degree with the vco gain variation. But one thing now suspect is may be the loop bandwidth too high, the loop bandwidth is 1 MHz. And the input frequency that give problem is 30 Mhz...any idea if the input frequency is 30 MHz, what is the max loop bandwidth can go? Will it cause problem with input frequency 30 MHz with the loop bandwidth 1 MHz? Thanks for your opinion.

Look like I already found the solution... i reduce the loop bandwidth to 500K... it work and no more ocsillation... what i can see is with small loop bandwidth, it suppress all high frequency noise.. and also i think it is not a ocsilation as suspect, but it is a high frequency noise and the amplitude is very large and only through small loop bandwidth can suppress it.

 

[jfyan]

Re: PLL phase margin

how about thetuning range of your VCO?
is there any change of your KVCO when doing these ?

yes, my vco gain do vary.. but i already simulate with Matlab which show phase margin still in the range of 45 to 50 degree with the vco gain variation. But one thing now suspect is may be the loop bandwidth too high, the loop bandwidth is 1 MHz. And the input frequency that give problem is 30 Mhz...any idea if the input frequency is 30 MHz, what is the max loop bandwidth can go? Will it cause problem with input frequency 30 MHz with the loop bandwidth 1 MHz? Thanks for your opinion.

hi,
in general, the bandwidth can be chosen to be 1/10 less than the input frequency. so it is okey in your case. however, if the loop bandwidth is too large, althougn is still less than 1/10 input frequency, you must take the loop delay into account, which will affect the pahse margin of the loop.
hope this help.
good luck.
jeff

 

[yellff]

Re: PLL phase margin

maybe the filter shd take into acount ,for example,enlarger the cap,or added
resistor to compensate the phase margin.