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Why pcb wires looks like loops?

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tpetar, you can trust edaboard members who are professionally equipped with high speed PCB design in this topic.

Serpentine trace patterns like the shown ones are added for length respectively signal delay matching puposes. They are primarly used in impedance matched connections, in other words the trace should be analyzed as a transmission line where the trace inductance is balanced with the capacitance.

Of course, the same shape can serve as lumped inductance under different conditions.

The present serpentine trace example shows a rough style, and I'm not sure if it's actually necessary for a pixel rate as low as 120 MHz. But the photo shows a least a broad idea of length matching.

FvM if You say that this is length matching for signal delay, I beleive You!

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I just received email with answer from Techtoys:

To keep traces the same length.
 
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This might be of interest.

Keith.
 

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Length matching.
All the major packages can do it and any DDR interface requires it. Its common place on a lot of PCB's these days.
 
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Tpetar, why did you not believe the rest of the forum members who were telling the OP (and you) that this was length matching?

I hope that you have leant something now as it is obvious that you did not know about length matching before this thread.
 

Tpetar, why did you not believe the rest of the forum members who were telling the OP (and you) that this was length matching?

I hope that you have leant something now as it is obvious that you did not know about length matching before this thread.

Of course I didnt know for that, but at first this serpentine looks like some inductors, but allocate lots of spaces, later I found on Internet some inductors in multilayer of PCB. I read usermanual of rev2 board and there is no this serpentine tracks, only straight lines, but in rev 3B they use it, I read that they multiply 10Mhz oscilator to 120MHz, realy I dont see purpose of this. But if manufacturer put that there, that is that. I saw similar PCB the same with serpentine like that but shorter, and tracks are not the same length, and no multilayer PCB. I trying to find this to show.

But should I say on edaboard can be learned lots of things, everyday one two new things.... for me edaboard is great learning source, just others idea or question for some problem can give you answer for something yours.
 

At the bus we are talking about, the highest frequency in my actual design is about 12Mhz, that is the pixel clock signal.
For signal generation, it uses an external crystal. The frequency is multiplied internally using a PLL so we can have several clocks (system clock, pixel clock, etc...). Depending on the design, the internal frequency can be very high (more than 100 Mhz). In this manner, programming several internal registers we can have different frequencies, so we can use different displays pannels with the same controller. Other controllers use also external SDRAM's (like epson S1D13517) with high bus frequencies derived from the PLL. That is the reason of the frequency multiplication.

hongphuc118, i haven´t designed the board... it is a comercial evaluation board...
 

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