PCB Layout design for PCIe

[engr_joni_ee]

I am running pre-layout simulation in LineSim in HyperLynx. I have attached the pre-layout schematic design created in LineSim. I am using IBIS AMI models to configure the Tx and Rx. I have run a sweep over the length of trace in 3rd layer. The simulation is passing for PCIe Gen 4 for a trace length 3 inch, 10 inch and also for 20 inch. I have enabled the option to remove non-functional part in the via and also the back drilling in the via. I am using high loss FR4 (Dk = 4.7 and Df = 0.02) to the simulations. The height and width in the eye diagram reduces when using 20 inch long trace in 3rd layer but still passing the criteria for PCIe Gen 4. Is that a surprise ? as we know that FR4 is high loss dielectric material and dielectric losses dominates the conductor losses beyond 4 GHz approximately but then how it passes PCIe Gen 4 ?

 

[engr_joni_ee]

Any comment on this please ?

 

[FvM]

I'm not surprized. What is the actual PCIe trace length range of your design?

 

[engr_joni_ee]

The actual trace in the design would be around 3 inches. But I am trying to find in simulation where if fails when using FR4 as dielectric material. I was running the simulation without any Tx/Rx noise in the beginning. When I added 2 % of UI as noise at Tx and also at Rx. It fails for even 10 inches long trace on the main routing 3rd layer. I do not know what are the realistic noise models for Tx and Rx. Where can I find those ?