Jun 17, 2021 #1 S sivaji.satya Newbie Joined Sep 28, 2020 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 18 After specifying Wire Load Model and constraints to a design (in1 is connected to inverter and inverter output is connected to Dflop input), wire delays for the below two commands are different. Why? >report_timing -from in1 -to reg1_reg/D -nets -input_pins >report_delay_calculation -from in1 -to inv1/A
After specifying Wire Load Model and constraints to a design (in1 is connected to inverter and inverter output is connected to Dflop input), wire delays for the below two commands are different. Why? >report_timing -from in1 -to reg1_reg/D -nets -input_pins >report_delay_calculation -from in1 -to inv1/A