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Why net delay calculation in report_timing and report_delay_calculation are different? - ASIC Synthesis(Synopsys DesignCompiler)

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sivaji.satya

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After specifying Wire Load Model and constraints to a design (in1 is connected to inverter and inverter output is connected to Dflop input), wire delays for the below two commands are different. Why?

>report_timing -from in1 -to reg1_reg/D -nets -input_pins
>report_delay_calculation -from in1 -to inv1/A
 

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