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Why minimum W/L of transistor is 3/2?

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amitjagtap

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hi all,
I want to some perfect reasons for "Why minimum W/L of transistor is 3λ/2λ ?"
It will be very helpful if the ans is with clarification.
Thanks in advance
 

renwl

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"minimum W/L of transistor is 3λ/2λ "?
where does it come from?
 

amitjagtap

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Based upon λ rules,which are applicable above 1um technology, the minimum transitor size can be 3λ/2λ, Why?
 

Alan_Nesta

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I've seen one 1.2um project inverter
nmos: w/l=1.1um/1.2um
pmos: w/l=2.2um/1.2um
 

tommydidi

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I never heard about it. Could you please show me where you found this -- "Based upon λ rules,which are applicable above 1um technology, the minimum transitor size can be 3λ/2λ" ? Thanks.
 

amitjagtap

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I have downloaded the following table from http://www.sm.luth.se/csee/courses/smd/099/scmos72.html
here mosis has given design rules.
SCMOS Layout Rules - Active
Rule Description ------------------------------------- Lambda
2.1 Minimum width - -------------------------------------------- 3
2.2 Minimum spacing - -----------------------------------3
2.3 Source/drain active to well edge - ----------------- -----5
[SUBM 6]
2.4 Substrate/well contact active to well edge - -------------3
2.5 Minimum spacing between active of different implant ---0 or 4

SCMOS Layout Rules - Poly

Rule Description ----------------------------------Lambda
3.1 Minimum width --------------------------------------2
3.2 Minimum spacing --------------------------------------2
[SUBM 3]
3.3 Minimum gate extension of active ------------------------2

In the above tables rule 2.1 shows minimum width for active is 3λ.
and rule 3.1 shows that minimum width for poly is 2λ.
 

tommydidi

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Hi amitjagtap,

Thank you for the information. From what you posted, it seems you are talking about the layout rules. Is 3*lambda/2*lambda has something to do with the process? It could be the specific foundary who sets this certain rule.
 

amitjagtap

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hi tommydidi
i'm talking about layout rules, but its not specific foundry rule.
I'm student doing M.Tech in VLSI. And we have followed lambda design rules for layout in Tanner Tool.
What i know is
1)lambda rules are different than submicron rules.
2) Lambda rules are applicable above 1um.
3)submicron rules are different for each foundry.

please clear me if i'm wrong.
Well, are you professional in VLSI design field?
Also I'm confused between model file and Technology file, are they same or different.
thanks
 

heng155

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model file is for your to simulate your circiut
Technology file is the define of your process layers, for you to draw the layout
Someone call drc lvs rce rule files Technology file, for you to verify your layout
 

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