Why it is preffered to have maximum no. of vias?

[mpkp123]

Hi all,
can any one tell me why in a layout it is always preffered to have maximum no. of vias though we know each via has some resistance associated with it and after a particular no. it is of no use to put more vias.
Then why we put maximum everytime

 

[hanm]

I think the reason you had understood.

 

[rajkumaru]

Hi mpkp123,
as hanm wrote that you had understood the reason. then lease can you let us know Why?????.

 

[karri]

There r two reason. one is to reduce the vias resistance which is around 5ohms. second it is good reliability

 

[hamdard]

By vias, you mean parallele tracks!
If I am getting the problem correctly, then the reason for parallel tracks is to lower the net resisrance of the track. Also the tracks are mae thick gor the same reason.

 

[chippi]

hi,

we put via's between two metals (which has some resistance), we add more via's to decrease the resistance ( resistance to the current flow) and thereby have a free flow of current in these metals.
now imagine, if u have two metals say, metal1 and metal2. and u just have a via between them, the current flows from metal1 to metal2 through just one via which increases the resistance to the current flow.
now if u have many via's , the current can flow between metals in parallel there by reducing the resistance to current flow.

hope this was convincing !

 

[shaikhsarfraz]

hi,
we use maximum number of vias to reduce the resistance and capacitance associated with them

thanks
sarfraz

 

[gafsos]

Hi 2 all,

There is something called DFM (design for manufacturing) whichb has as goal :
Maximize yield
Ensure stable yields
Proactive designs
Steep yield learning-curve / competitive time-to-market
so it's recommanded to Implement contact ia redundancy many time as possible and try to double them

Salam, g(at)fsos

 

[pixel]

Here is the interesting question: If we want to reduce resistance we could use solid line. Why are preffered vias instead of solid line?
You have explanation here:

 

[stuck_adc]

the most common type of failure during IC fabrication is the via failure -
it can be due to :- random defect or void due to electromigration...

thus to improve yield we go for more than 1 via, it is a added advantage that multiple vias reduce the resistance and capacitance.

this was not needed till 180nm, but for 90nm and higher it is a neccesity.....even foundry recommends this type of layout style......to combat random defects at time of manufacturing.