Why it has a constant 1 value?

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horzonbluz

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constant(1)

Hi, my friends. When i run DFT, it reports there are two clock gating cell have constant 1 value output.
Usually in the test condition, the test_se signal will and the Clock signal, that is to say test_se && clock. Why the report said the clock gating cell has constant 1 value?
I don't know how to handle this problem. Who can help me and give me some advice?
 

set_test_hold


If the clock-gating cell mean Latch than latch enable signal?
I think you have set_test_hold 1 test_mode.
may it result in the information.
 

Hi, haosg.
I think the DC tool will not treat the clock gating cell as a "Latch". Because it usually has clock_gating_integrated_cell attribution.
The second i don't know why not "set_test_hold 1 TEST_MODE". In DFT, we must set this. I use TEST_SE signal as test control signal in clock gating cell.
And last in my report, this is a violation. So i must solve it.
Below is my setting for TEST_MODE signal:
set_dft_signal test_mode -port TEST_MODE;
set_test_hold 1 TEST_MODE".
 

My opinion is you should not connect test_se to the clock gating cell. Instead you
should implement a addition test mode bypass control input and connect this signal to
test_se pin of your clock gating cell.
 

Hi, kctang. Do you have used this method in your codes?
In clock gating cell, we can use TESE_SE or TEST_MODE as the test control signal. Usually we choice the TEST_SE. If we want to gating a function module, we will use a clock gating with a test pin controlled by TEST_MODE. Why you use this method?
 

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