Why is this excellent high-side FET drive method for SMPS never mentioned?

[treez]

Hello,
The following article on Mosfet gate drive methods is amongst the world’s finest. Why then, does Balogh not mention the method of using an external Gate drive supply SMPS? As you know, this method means having isolated outputs which simply feed a gate drive IC next to the high side FET. A digital isolator couples the gate drive signal to the high side gate driver.

Mosfet Gate drive article:
http://www.radio-sensors.se/download/gate-driver2.pdf

ltspice simulation and pdf of excellent fet drive method attached

 

[Easy peasy]

This is actually pretty common on a lot of inverters....

 

[treez]

Thanks, yes, very common in inverters as I found when working in electric drives business....which are, as you know, much lower frequency than SMPS. Why , I wonder, is it not common in SMPS, running at higher frequency?

 

[Easy peasy]

A good gate drive transformer design works well up to 400kHz, and needs less parts....

 

[treez]

Thanks,
The problem with pulse transformer gate drive is the following…..

1..You always need to drive the lower FETs through pulse transformers too, in order to get the same propagation delay, so you need more coils in the former.
2A….The source of the gate drive current is on the primary side of the pulse transformer, so that high current pulse has to traverse a potentially long bit of PCB to get to the FET gate. (with the method of post #1, there can be a gate driver right next to the FET itself, so the high pulse current can be in a tiny loop)
2B….Two gates can be driven from the same former, however, this means your gate drive has to be able to provide all that extra current to actually adequately drive those two FETs from the one driver. With the method of post #1, each FET can have its own dedicated drive chip.
3….Pulse transformer gate drives virtually always need a turn-off PNP to be included, so there’s extra parts.
4….Pulse transformers for FET gate drives need to be precision engineered, so that they have absolute minimum leakage inductance. If your winder has a bad day when winding them, then your SMPS batch may suffer too high switching losses and fail.
Its noteable how even tiny amounts of leakage inductance in a pulse transformer gate drive can really slow up the switching transient of the FET.
5….Pulse transformers for gate drives are rarely if ever available to your particular spec off-the-shelf, you virtually always have to get them custom wound.
6…Pulse transformer gate drives always need series resistance to be included in order to prevent ringing with the leakage inductance of the pulse transformer. There needs to be a resistor in both primary and secondary sides of the pulse transformer. This resistance always ends up being bigger than you would like, and means that your FET’s switching transients are always slower than you would like, meaning you get more switching losses.
7….If the method of post #1 is used, then you can use an 1EDI20N fet driver right next to the fet, and get absolute optimal turn off and turn on of the FET. (the 1EDI20N FET driver has separate pins for turn off and turn on.)

1EDI20N gate driver:
https://www.infineon.com/dgdl/Infin...N.pdf?fileId=5546d4614755559a014790299add6112

.....after all this, I am amazed that nobody is using the method of post #1 with SMPS.
Attached simulation shows a ltspice sim of Pulse transformer solution

 

[Easy peasy]

your diagram shows all the 220 ohm resistors shorted...

leakage needs to be controlled on GD xfmrs, but we have had good results up to 400kHz with GD Tx for high side only, and no series resistors, 30nS rise times (0-100%) and slightly quicker fall times on the gates, yes you need to provide current but its not too hard with good semi's...

 

[treez]

Thankyou , yes indeed, shorted out, here are the corrected versions.

 

[D.A.(Tony)Stewart]

The lag in forward conversion of the power to driver may result in some overshoot on step turn on regulation under some conditions of low input V , high current load, unless current ramp soft start is used.

 

[treez]

Thanks, also, the method of post#1 really needs resistors adding to the isolated high side secondaries, as shown ringed in the below picture. This is to cut down unwanted pulses of current going through the interwinding capacitance of the transformer as the bridge voltage transitions up and down repeatedly.

Its noteable how this is easily done with the transformer method of post#1…it is much less easily done with pulse transformers, -since with pulse transformers, adding such resistors slows up the switching transition unwontedly.

- - - Updated - - -

leakage needs to be controlled on GD xfmrs, but we have had good results up to 400kHz with GD Tx for high side only, and no series resistors, 30nS rise times (0-100%) and slightly quicker fall times on the gates,

Thanks, but I imagine that there is some rather special and potentially expensive pulse transformer winding process going on here? -As well as high dependency on excellent winding staff to do the job that well, and check that it really has been done that well.

 

[treez]

Do you think the following digital isolator will be able to handle the dv/dt that it will see in the application of the attached pdf schematic of post #1
Digital isolator datasheet: (35 to 50V/ns transient immunity)
https://www.silabs.com/Support Documents/TechnicalDocs/Si861x-2x.pdf

 

[Easy peasy]

Simply winding 2 x TIW 0.3/0.5mm wires bifilar on a toroidal core gives adequate performance up to 400kHz.

 

[treez]

thanks, the thing is, in our 3.8kw LLC stage we want to turn the FET(s) off super quickly to reduce turn off switching loss. -Thus we will have a 1EDI60N fet driver right next to the high side FET, and we need a high side supply for that. I realise we could have a turn-off-PNP right next to the FET, and they operate in common collector mode, so should switch quickly, however, I believe BJTs never switch really quickly, so we would need the FET driver right next to the FET.
Not only this, but those fast switching PNP's from eg diodes.com have a tolerance on Hfe at high current, and other parameters, so in the worst case tolerance batch, they won't operate that well....but with a fet drive ic, we always get good performance.

 

[Easy peasy]

Cheaper to use a pnp xtor with schottky from collector to base, this is what we use at 400k, the circuit is the thing, but a driver IC is certainly one solution, beware internal dissipation at high freq's and there are a few that suffer high internal Vspikes even with good de-coupling, we have investigated a few of these failures, can't see it with a scope...! have to model it to show failure mode - very tricky - except the failures are real...

 

[treez]

thanks, we will look out for that, another point I remember when working at a Travelling Wave tube PSU place, the engineer told me that he removed the shunt zeners from the secondary of the high side pulse transformer secondary, and the PSU blew up very quickly, so he put them back for the next one. I do remember their most Senior Engineer telling me how they liked to minimise the amount of circuitry (IC's etc) that they have in high side supplies.

I also remember an old onsemi.com app note, which has now vanished from their site, which used to warn of the danger of the "bridge" pin of the NCP5181 bootstrap driver IC ringing below GND , and they recommended a diode from BRIDGE to GND pins, as well as a 10r or so resistor to mitigate this.

 

[treez]

Hello,
This is related to the above , but not concerning it....
Hello,
Do you agree that the attached high side FET drive method is massively better than just using a pulse transformer?

As you see, the method uses the pulse transformer as merely to pass through the gate drive “signal”, and the fet drive IC in the high side does all the high current pulse stuff. (the bit of power required is also “gently” passed through the pulse transformer, and not as some ‘neck-braking’, high di/dt pulse like in a “normal” pulse transformer drive.)

The advantage is that you don’t suffer from leakage in the pulse transformer, so you can wind it to a loose spec.
Also, the high side FET drive IC holds the top fet hard off (due to its low impedance current sink output) such that it never comes on spuriously.
PNP turn off stages are particularly poor at holding FETs “hard off”. With the turn-off PNP you simply end up with shoot through current happening whenever the low side FET of a leg turns on.

Ltspice simulation and schematic attached.
Surely you agree on the superiority of this high side fet drive method?

 

[treez]

leakage needs to be controlled on GD xfmrs, but we have had good results up to 400kHz with GD Tx for high side only, and no series resistors, 30nS rise times (0-100%) and slightly quicker fall times on the gates, yes you need to provide current but its not too hard with good semi's...

The above quote, from post #6, says that "no series resistors" were used in a high side FET gate drive transformer (GDT), where duty cycle was 0-100%.....how can this be possible without getting excessive ringing between the GDT magnetising inductance and the series capacitor?

Second paragraph below Figue 2 of the following article tells of the danger of the GDT magnetising inductance ringing with the series capacitor...surely this needs series resistors to damp it? .......

"Gate Drive Transformers vs. Fully Integrated Isolators in Isolated DC-DC Power Converters"
https://www.eetimes.com/document.asp?doc_id=1273338

//QUOTE from the above article//Care should be taken in applications where the duty cycle can change rapidly, such as transient response, which can result in erratic operation or damage. As the bias across the coupling capacitor is changing (due to a change in duty cycle) the capacitor can ring with the transformer magnetizing inductance. //UNQUOTE//

 

[Easy peasy]

parallel RC snubbers to the gate-source are possible to damp ringing - if you have it - also suitably rated zeners....

- - - Updated - - -

for fixed 50% (49%) gate drive, many ringing issues disappear...

 

[treez]

for fixed 50% (49%) gate drive, many ringing issues disappear...

Thankyou, and that is very poignant indeed, because it is a very good reason why a phase shift full bridge SMPS is better than a plain full bridge SMPS, because PSFB has fixed 50% duty...even in no load.
And a very good reason why LLC also shines out.