Why the obsession with output ripple voltage of SMPS?

[cupoftea]

Hi,
Why is it that most Engineering companies who are looking to get a Switch Mode Power Supply designed for them
are only interested in the voltage ripple on the output volts?
They fear that an SMPS will destroy the operation of their system due to the SMPS noise.
As long as an SMPS has enough capacitance so that the output caps are not over-ripple currented, then the ripple that you get will generally be
fine and not too noisy in 98+% of cases.

Even 3v3 microcontroller or FPGA rails don't need to have ripple less than 200mvpkpk in general. As long as any analog reference voltage is ripple
free then its fine.

Yes you get some inamps that need super low ripple but they just use a low power rail which can be heavily filtered...so the ripple on the
main incoming power rail is irrelevant.

The actual noise problem of SMPS is the common mode noise that they give off...and this cant be measured on the scope.

So why is the world so obsessed with SMPS output ripple voltage specs?

 

[andre_luis]

In addition to the SMPS intrinsic output swing, there will be many other devices on the board adding their our contribution to degrade the power bus; since these artifacts are assynced each other the interference could either cancel or add, so why not concern on that?

 

[dick_freebird]

Because every damn thing has a radio on it now?

Because they don't know what aspect of delivered noise matters, so they fixate on the one that's published?

 

[Easy peasy]

Not to mention CM noise to earth ! I like a well engineered psu, for plain battery charging 100mV rms diff noise is fine, < 1V CM - for a bench psu < 5mV rms ( @ full power ) & < 50mV CM.

 

[mtwieg]

Because every damn thing has a radio on it now?

Because they don't know what aspect of delivered noise matters, so they fixate on the one that's published?

This is basically it.

There is no straightforward ways of characterizing noise/ripple/EMI in a way that allows one to ensure that a power supply will work with a given load (like a radio or whatever). "Ripple" is one of the only metrics which can be measured in a straightforward manner, and it's better than nothing I guess.

I've seen some companies provide test data on radiated/conducted EMI for power supplies, but that's quite rare.

Even 3v3 microcontroller or FPGA rails don't need to have ripple less than 200mvpkpk in general. As long as any analog reference voltage is ripple
free then its fine.

Good luck if the supply for your PLLs has this much ripple on it.

 

[crutschow]

The high frequency ripple of a switching supply may not be a problem for digital circuits, but if there's an analog circuit anywhere around, it will find that ripple.

 

[D.A.(Tony)Stewart]

CMOS inverters have poor PSRR and Vdd ripple adds to edge modulation which may affect marginal timing or worse multiple transitions. This is critical for SERDES, PLL ccts and others.

 

[cupoftea]

CMOS inverters

Thanks , you mean as in the things that give a logic "1" or "0" in computor processors or microcontrollers?
Guess they dont all have a Schmidt Trigger with them to stop multiple transitions.?

So if it jitters a bit in going from logic 1 to 0 (or viceversa) then thats bad because of the extra switching loss in the processor?...or from an electrical noise viewpoint?...presumably even with bad ripple on the Vcc, the jitter would all be over within 50ns anyway?

And in most cases, the Micro Vcc rail "would" be heavily filtered without needing to heavily filter the PSU output bus rail.

When we're talking PLLs etc we are taking 5V rails and below.....no 9V, 12V or 24V or 36V or 48V rail would likely ever need a low ripple spec.

 

[dick_freebird]

Prop delay has a supply dependence.

Thus if the supply varies so will delay.

When supply varies in "signal time" then so does delay. Cycle to cycle delay variation is your "jitter" and the "jitter" steals from your reliable open eye interval at next register.

The edge-rate dV/dt is your transform of voltage ripple to "time ripple" - dt/dV - with the gate delay dependence also varying besides its input-slew-to-threshold component.

A Schmitt helps this none. It will suppress chatter on slow noisy edges (where input, ground and supply noise are below hysteresis window). But wider input band offers more jitter for same supply noise and same dV/dt as dV is more

 

[D.A.(Tony)Stewart]

CMOS inverters

> Thanks , you mean as in the things that give a logic "1" or "0" in computor processors or microcontrollers?

Yes when I say "CMOS inverters", that includes all high speed digital logic included in computers, which becomes analog when things can go wrong in a fraction of a bit.

Falstad's logic inverters are ideal and the FETs have no capacitance but can have any Vt and Beta ( Ron, Id) you choose, to simulate any FET with static properties. But for dynamic properties one must include Ciss, Coss which comes from Cgs, Cds, Cdg. But if you put any two caps in parallel , that implies infinite current on any voltage difference which is a code violation, so at least one must have some resistance.

To make an ideal CMOS inverter logic symbol current limited RdsOn = Vol/Io from the datasheet @ 25'C @ Vdd
THus each family has a similar spec with RdsOn having a wide tolerance due to the same >2:1 Vt tolerances in all FETs.

Whereas other simulators like LTspice use a model with nominal values and not worse case.

Falstad examples /w values in options. adding driver resistance then add ESD protection, and then it starts to look more linear.

But if you do not know all the variables of logic inverters and tolerances, then like LTspice, you avoid supporting "Analogic" logic device characteristics and leave it up to 3rd parties or user groups.

All simulations are only as good as you show the reality of a good layout and important RLC component characteristics after you get past the basics.