JFET is about the simplest structure you can make. It
has some usually-undersirable features, such as needing
to drive the gate beyong the source rail (which voltage
you may not have, or care to create). This relegates
them to applications such as cascode guard transistor
(see some GaN power devices doing this, GaN FET over
NMOS switch) and op amp front ends where you can
spec some headroom to accommodate the pinchoff.
I had to design some JFET based analog switch / mux
products once, and it was a lot messier than a CMOS
switch. A S/H too, which ended up needing a lot of
fancy gate drive control to minimze the hold pedestal.
Why? Because we had no CMOS technology suited to
the application (don't ask).
You don't need fine lithography to define the gate, the
working voltage will define that upward from your node's
capability most likely. Pinchoff and BV come from gate L
and the channel doping.
Frquency response tends to be poor if you use the back
gate to increase gm, because now all that capacitance
(or a large chunk) is Cdg, not Cds. But you can get some
surprisingly good RF performance out of a short channel
MESFET on thin SOI. Of course your in-house technology
mavens will barf all over its variability and so on, because
improving it would require some effort on their part. But
I've seen grad students accomplish this in my former
foundry, where my Technology (so-called) group would
not even be convinced to try.
And that is often the bottom line - somebody in a position to
say "no", decides they don't care to support a fringe-application
device in manufacturing and CAD. If you can't make their Dad
spank them (by showing him the money), it won't get blessed
(probably, not even built).